Final-stage (FS) topology

Figure 2 shows the FS topology and output network of the proposed DOPA. The FSs are realized in push-pull configuration with transistors V1(A,B) and V2(A,B) switching the output voltage on and off between + V _dd and ground. The blocks at the input represent the driver stages. This topology is commonly used for voltage-mode class-D/S PAs [Reference Nakamizo, Mukai, Shinjo and Gheidi2, Reference Wentzel, Chevtchenko, Kurpas and Heinrich4]. The output network is composed of a reconstruction filter with L_{filt (A,B)} and C_filt and the load resistance R_load. On principle, the circuit operates in the same way as the one described in [Reference Ding, Hur, Banerjee, Hezar and Haroun8]. But for the most crucial operation between 0° and 180° phase shift we propose an output network that is modified compared to [Reference Ding, Hur, Banerjee, Hezar and Haroun8], in order to achieve higher efficiency: An additional inductor L_aux is introduced for fully or partly resonant commutation (ReCo) of the center-tap (CT) voltages. When the output power is extremely close to zero, resonant commutation could be achieved only by L_{filt (A)} and L_{filt (B)}. In all other cases, ReCo cannot be achieved for amplifier branch B without L_aux.

Fig. 2.

Circuit topology of the proposed digital outphasing PA.

Optimizing efficiency and resonant commutation

The ReCo at the FS transistors (V1/2 (A/B) in Fig. 2) is important for a low-loss design [Reference Ding, Hur, Banerjee, Hezar and Haroun8], since in the hard-switched case [Reference Wentzel, Chevtchenko, Kurpas and Heinrich4] remarkable capacitive switching losses occur. Effective output capacitances of used FS transistors are in total 1.4 pF. In case of hard-switching the transistors with a clock frequency of 800 MHz and 30 V amplitude, power losses caused by recharging the output capacitances of the four FS transistors reach 1 W. With a maximum output power of 5.8 W, FS drain efficiency at 10 dB PBO would be limited to 35%, without accounting for any other losses. A partly resonant commutation improves this situation. If 3/4 of the voltage swing is accomplished in a resonant way, for instance, efficiency grows to 68%. On the other hand, ohmic losses (on-state losses through R_{ds _on} of the FS transistors) increase due to an additional current through L_aux (see Fig. 2). We propose to use partly ReCo only, which lowers this additional current and also minimizes the capacitive switching losses P_loss strongly enough to improve efficiency.

In the design process, the range of high FS drain efficiency η_drain can be determined by the key circuit elements such as the FS transistor size and the value of L_aux. The basis for estimating the crucial range of PBO is the power probability density distribution. If this function is multiplied with η_drain as a function of output power and integrated over the output power range we obtain an average FS drain efficiency, which is to be maximized [Reference Wolff, Heinrich and Bengtsson13]. For a 10 dB PAPR signal, for example, high η_drain must be reached in the PBO range from 4 to 15 dB.

To vary the output power, in principle only the phase between both amplifier branches has to be chosen appropriately. In order to further improve efficiency, we apply a pulse-width modulation (PWM), too, i.e., we vary the duty cycle on all signal inputs. This is only applied additionally to support and guarantee zero-voltage switching (ZVS) at the output to minimize the losses. If one solely varies duty cycle the outphasing concept does not work, no resonant commutation is realized and the output network needs to be rebuilt. Figure 3(a) shows simulated timing diagrams for 0, 6, and 10 dB PBO. Moreover, the measured timing diagrams for nearly full-power operation (upper part) and 10 dB PBO (lower part) in both PA branches is displayed in Fig. 3(b). Rising and falling slopes of the CT voltage are slightly asymmetric. This is because the positive high-side driver supply represents an additional load to the CT node. The input duty cycle in the measurements, e.g. for 0, 6, and 10 dB PBO, have been set to 45, 25, and again 25%, respectively.

Fig. 3.

(a) Simulated oscillograms of center-tap (CT) and output voltages for maximum output power (0 dB PBO), 6 dB PBO and 10 dB PBO; f_clock = 800 MHz; V_dd = 30 V; input duty cycles of PWM – 0 dB: 45%, 6 dB: 34%, 10 dB: 30%. (b) Measured oscillograms of center-tap (CT) voltages for nearly maximum output power (upper) and in 10 dB PBO (lower); f_{cloc k} = 800 MHz; V_dd = 30 V; input duty cycles PWM – 0 dB: 45%, 10 dB: 25%.

In terms of 10 dB PBO measurement, e.g., the input duty cycle was set to be 25% at the pulse generator. Checking the voltage waveform after the final–stage (see above, lower Fig. 3(b)) one calculates a duty cycle shift to around 32% because of different driver speed between full-scale and PBO operation. To clarify this, one can check one period for CT_A curve which is around 1.25 ns, for example. The absolute on-time (voltage is high (around 30 V)) can be determined to be 0.4 ns. This leads to the above-mentioned duty cycle. Additionally, the significant rise and fall times make the pulses look wider.

Driver circuits

The digital modulator (cp. Fig. 1) generates an input bit sequence for the digital PA with a voltage swing of usually up to 1 V_pp due to a commonly used logic with low breakdown voltages based on SiGe or comparable. As GaN-HEMTs require an input voltage swing of at least 5 V_pp to completely switch on (V_gs = + 1 V) or off (V_gs = −4 V) a first preamplifier stage must be realized so that the GaN outphasing PA stage can work in digital operation. For the reason of simplicity and as no CMOS technology was available in our case we designed and realized a voltage level-shifter in source configuration on our Ferdinand-Braun-Institut (FBH) 0.25 μm GaN-HEMT process shown in Fig. 4.

Fig. 4.

Circuit diagram (left) and chip photo (right) of the realized preamplifiers to amplify modulator output (1 V_pp) to required outphasing PA input voltage swing (5 V_pp); chip size (2 PAs on 1 chip): 1.1 × 0.65 mm².

Due to the small input voltage swing coming from the modulator output this preamplifier works like an analog class-A PA. Thus, the efficiency is quite low as each of the required four preamplifiers consumes 260 mW of power. We have to state that the power consumption of these preamplifiers (4 × 260 mW in total) is not included in the total efficiency values presented in the section “Realization and Measurement Results”. But it is a required tool for proper broadband driving of the digital outphasing PA. Moreover, the preamplifiers are even more efficient than usual laboratory preamplifiers based on travelling wave amplifiers. But, as already mentioned, e.g., in a final module setup one would realize the preamplifier in an extended CMOS process. However, the design is challenging as an input capacitance of around 0.5 pF must be driven with pulses showing rise/fall times in the 100 ps range.

Now, with enough input voltage swing, all the following stages including push-pull FS can operate as digital PAs. The required highly efficient digital-working drivers for the outphasing PA push-pull FSs are described in the following.

The positive supply of the upper drivers is connected to their adjacent CT node. As all transistors of the digital PA are normally-on types and no complementary GaN FETs are available, efficient driving of the push-pull FSs is very challenging. The drivers for the upper and lower FS transistor are designed for fast switching of the gates with low power consumption. All drivers are in push-pull configuration. Figure 5 shows the circuit diagrams.

Fig. 5.

Proposed driver circuits for low-side (left) and high-side (right) final-stage transistor integrated on the digital outphasing PA MMIC. R1L and V1L are not part of MMIC.

The low side driver (Fig. 5, left) has a commonly used topology. The Z-diode V1L realizes the potential shift for the different gate bias of VL3 compared to VL5. The high side driver (Fig. 5, right) has no power wasting pull-up resistor connected to the positive supply of the final stage. VgH and VeH are DC biased, INH is the signal input. Parts of the predriver for the lower push-pull transistor (V5H) are closely related to a high-speed switching stage published in [Reference Disserand, Bouysse, Martin, Quéré, Jardel and Lapierre14].

Assuming INH is low, V4H is in the high ohmic state (OFF), and no current flows through R5H. As all transistors, V5H is of normally-on type. Thus, with its gate-source voltage being zero, V5H is ON. Assuming a voltage on the source of V5H which is negative against the CT voltage, V5H pulls the gate-source voltage of the adjacent FS transistor to a negative value and thus the FS transistor is switched OFF. At the same time – INH is low – V1H is ON, driving V2H and V3H into OFF-State. Current flows from the source of V5H to the drain (reverse mode) and through R3H, R2H, V1H to INH. This current brings the voltage between the source of V5H and the CT node to negative values. The DC blocking capacitor C1H keeps this voltage.

Assuming now that INH is high, then V4H is ON. Current flows through R5H and C1H, driving V5H into OFF-state and loading C1H further negative. V1H in this state is OFF, no current flows through R2H and R3H, and V2H and V3H are ON. CT is connected to the gate of FS transistor via V3H, which is ON, too.

As described, there are two paths through which C1H is charged negative versus CT. The opposite current flows when V5H is ON and the gate of the FS transistor is pulled to a negative voltage. Both currents have to be balanced.

This high-side driver limits the negative gate-source voltages of all its transistors by controlling them via the resistors R1H and R4H and the applied voltages VGH, INH, and VeH, independently from the FS supply. This keeps negative gate-source voltage of all transistors in a safe range, even for high FS supply voltages.

Realization

The realized DOPA MMIC is shown in Fig. 6. It was fabricated using a dedicated 0.25 μm GaN HEMT process at FBH. The MMIC layout follows a compact digital approach. The digital PA function requires a broadband operation and fast switching, so the conventional analog PA design with usually narrowband and bulky reactive matching networks and transmission-line elements as interconnects is not required. Therefore, it is abandoned in favour of a lumped-element circuitry without any impedance reference.

Fig. 6.

Chip photograph of the realized GaN digital outphasing PA MMIC with connecting gold bond-wires; chip size: 2.1 × 1.9 mm².

The chip was mounted on a copper heat sink and input as well as bias, preamplifiers and output circuitry (L_{filt (A,B)}, C_filt, L_aux, C_{DC -block}) were soldered on a 0.25 mm Rogers 4003C PCB laminate. The module exhibits an overall size of 50 × 45 mm² and is shown in Fig. 7. The 800 MHz output filter uses Coilcraft air-core inductors (33 nH) from 1111SQ-series and a capacitor from ATC's 600S series (1.5 pF). The inductor L_aux is also 33 nH and from the same Coilcraft series as the filter coils.

Fig. 7.

The realized digital outphasing PA module; size: 50 × 45 mm².

In order to suppress ringing effects arising with bond-wire and input line lengths due to connection between modulator output, preamplifier chips and main outphasing PA MMIC (see Fig. 6) very small 1 nF surface-mounted device (SMD) DC blocking capacitors with 008004 case size (250 × 125 × 125 μm³) from Taiyo Yuden have been glued directly on the preamp GaN-MMIC which is shown in Fig. 4 (left) and Fig. 8. From schematic in Fig. 4 (left) one observes that the additional blocking capacitor is placed in parallel to the on-chip 16 pF MIM caps. This opens up completely new possibilities with regard to short connected RF blocking in the integrated microwave or even mm-wave solutions for future applications.

Fig. 8.

Photograph of preamplifier GaN-MMIC from Fig. 4 with on-chip glued 008004 SMD DC blocking capacitors (1 nF) from Taiyo Yuden.

3D Electromagnetic (EM) simulation of output inductors

As described in the previous sections the output network (cp. Section “FS Topology” and “Realization”) is a very important and sensitive part in the outphasing PA setup as it needs to provide the right characteristic in order to reach the targeted partly resonant commutation and ZVS for optimum operation. Thus, it is necessary to have an insight into the real output network and to fully model it for accurate simulation. Therefore, the coils in the output network (cp. Figs 2 and 7) and their interaction are modelled with a full 3D EM simulation in CST Studio [15]. The coil models provided by the manufacturer are not used, because the shape of the coils on the circuits deviates from the original shape. Moreover, the coil models from the manufacturer do not account for mutual coupling of coils close to each other.

Two scenarios are investigated using CST Studio Suite [15]: First, a single coil representing L _aux in Fig. 2 is considered. Second, two coils which are translated by 5.6 mm in lateral direction as shown in Fig. 9 (top) are characterized. These coils represent L _filt(A) and L _filt(B) in Fig. 2. All structures are located on a substrate and are discretized with a tetrahedral mesh. The computational domain is chosen to be sufficiently large so that fringing fields are modelled appropriately. Material losses are not directly considered in the 3D EM model but can be included in the discrete circuit diagram using analytical loss estimations.

Fig. 9.

Computational model of two coupled coils as an example (top) and exemplary static B-field distribution for 1 coil (bottom). Both coils are placed on Rogers 4003C PCB substrate.

The boundary conditions of the 3D EM models are set everywhere on open except at the lower boundary which is touching the ground metallization. At this lower boundary, a perfect electric conducting boundary condition is enforced. All coils are excited by means of face ports located in the substrate between the pads and the ground metallization. The single coil is considered as network with two ports, whereas the coupled two coils are modelled as network with four ports. The frequency-domain solver of [15] is employed to determine 2 × 2 and 4 × 4 scattering and impedance matrices of each scenario, respectively. The solver delivers the aforementioned network matrices sampled on frequencies from 50 MHz to 20 GHz since switching of the outphasing PA is connected to higher harmonics.

For both scenarios discrete equivalent circuits are created which model the dynamical coil properties arising from the 3D EM simulations. The topologies of the equivalent circuits result from experience. The properties of the discrete components are determined by a nonlinear optimization, i.e. the properties of the equivalent circuits are chosen such that the deviations between the network matrices of the discrete equivalent circuits and the full 3D EM simulations are small. Figure 10 depicts the equivalent circuit for a single coil as an example. The parameters L_port and C_pad are determined by means of a 3D EM simulation of solely the substrate with the pads and the ground metallization, i.e. no coil is present.

Fig. 10.

Discrete equivalent circuit of a single coil. The total inductance of the coil is given by L_all whereas the parameter wL acts as weighting to move the inductance to the symmetry plane (wL = 0) of the circuit or away from the plane (wL = 1).

Figure 11 presents the comparison between 3D EM simulation and the equivalent circuit diagram of one coil. The curves show the absolute values of Z ₁₁ and Z ₁₂ in a logarithmic plot. Note that Z ₁₁ = Z ₂₂ and Z ₁₂ = Z ₂₁ holds on account of the symmetry and of the reciprocity of the structure. Both curves show a good agreement.

Fig. 11.

Comparison of the impedance parameters of the 3D EM simulated coil (blue) and the corresponding equivalent circuit diagram (red). Both curves show a reasonable agreement over the entire frequency interval.

Both, the discrete equivalent model for a single coil (refer to Fig. 10) and the model for two coupled coils (not shown) are embedded into a complete circuit model of the outphasing PA.

First, the coil models are combined with the used capacitors (C _filt, C _DC-block) to simulate the S-parameters and input impedance characteristics of the real outphasing output network (cp. Fig. 2) alone. Figure 12 shows the simulated network including port definitions.

Fig. 12.

Simulated outphasing output network including port definitions (1, 2).

As already mentioned material losses are not considered in the CST model. On account of the skin effect, the material losses are frequency dependent. However, we modelled the losses with a constant resistivity of 0.3 Ω. This constant value is a mean value for the frequency-dependent resistivity in the considered frequency range and is therefore considered to be a good compromise. Figure 13 shows the simulated input reflection coefficients (S _11/22) and input impedance characteristic (Z _11/22) from 0 to 4 GHz.

Fig. 13.

Simulated input reflection coefficients (top) and input impedance characteristic (bottom) for outphasing output network between 0 … 4 GHz using the extracted model for output network coils from EM simulation; reference impedances at ports 1/2: 64 Ω.

One clearly observes the best matching in terms of input reflection coefficient from the S-parameters in the 800 MHz range, i.e., the clock frequency band chosen for the measurements (see next section). The reference impedance at the input ports is set to 64 Ω. This represents the optimum input impedance Z _opt for the used GaN-HEMTs in the FS for a maximum drain supply voltage V _{DD_max} of 60 V and a maximum drain current I_{D _max} of 0.6 A. As the outphasing PA branches are excited in even-mode one must take care of the even-mode impedance Z_even which should be half the value of Z_opt, i.e., around 32 Ω. This is in contrast to the odd-mode which has to be suppressed by comparable high impedance (Z_odd >> Z_opt). The Z_opt for the used FS devices with V_{DD _max} and I_{D _max} is calculated as follows:

(1)$$Z_{opt} = \displaystyle{1 \over 2}\;\displaystyle{{k_{mod} \times \;V_{DD\_max}} \over {I_{D\_max}\;}}. $$

The output voltage amplitude for the push-pull FS configuration (voltage-mode) used in the DOPA is the fundamental component of a square-wave shaped output signal with ±V_{DD _max}/2. The output current is sinusoidal with maximum amplitude I_{D _max}. The voltage at the series output resonator with a certain load resistance R_L is the spectral content of the pulse sequence at (ideally only) the signal frequency according to the modulation used. Therefore we introduce the factor k_mod, which refers to amplitudes, not powers. The factor k_mod denotes the amplitude coding efficiency for the used modulation scheme and is a scaling factor of V_{DD _max}. For example, in terms of a simple PWM rectangular signal with 50% duty-cycle k_mod is equal to 4/π, which represents the prefactor of the first component of the Fourier series.

In Fig. 13 (top) both input reflection coefficients differ due to the additional L_aux – C_{DC -block} network at port number 2 (cp. Fig. 12). This is required to support resonant commutation (cp. the section “FS Topology”). In branch 1 (S ₁₁) the input matching is better than 11 dB whereas in branch 2 (S ₂₂) the input matching is only around 7 dB. This translates also in different impedance characteristics (Fig. 13, bottom). The input impedances at 800 MHz show values of 59 Ω at port 1 and 65 Ω at port 2, respectively. The appropriate even-mode impedance Z_even is 24 Ω. Simulated Z_odd is sufficiently high with 271 Ω.

Ideally one should provide Z_opt at the clock frequency to the FS while very high impedances need to be realized out of band. In both characteristics in Fig. 13 one observes very low impedance around 200 to 300 MHz. This arises due to the unbalance introduced by the additional ReCo support circuit (L_aux – C_{DC -block}) at port 2. It may influence performance as spectral components in this region are not properly reflected back into the outphasing circuit. Moreover, the simulated input impedance for branch 1 is too low compared to Z_opt (64 Ω). This means that the FS transistors will reach too early, i.e., at a lower drain supply voltage, the current saturation region and thus cannot reach the ideal operation area (V_{DD _max}, I_{D _max}).

To have a preview we simulated the entire outphasing circuit with the coil models in the output stage. For example, at full-scale input, the PA reached a simulated maximum output power of 5.7 W at 30 V drain supply with a total efficiency of 60%. Mean drain current through FSs was 286 mA, which means that current peaks close to I_{D _max} of 600 mA may arise. At 10 dB PBO the efficiency drops down to 25%. From simulation one can derive that due to the lower input impedance as well as Z_even provided by the output network to the FS devices an efficient operating area in terms of maximum current is around 30 V only.

Measurements

All measurements were carried out using an 800 MHz single-tone pulse-width modulated (PWM) input signal. For outphasing operation the phase between the amplifier branches was varied and additionally, the duty cycles for each FS transistor were adjusted, covering the range from 45% for maximum output power P_out down to 25% for high PBO.

Figure 14 presents the simulated and measured results for overall efficiency η_tot as well as for simulated FS drain efficiency η_drain as a function of PBO at a supply voltage V_DD of 30 V. The overall efficiency η_tot includes final stages and drivers, i.e., the full circuit shown in Fig. 2. Again, we must emphasize that the analog (class-A) preamplifiers required to generate the 5 V_pp input voltage swing for the GaN-HEMTs in the outphasing PA to fully switch on and off are not included in the total efficiency calculation (see Section “Driver Circuits”).

Fig. 14.

Measured and simulated overall efficiency η_tot as well as simulated final-stage drain efficiency η_drain vs. power back-off; f_clock = 800 MHz, V_dd = 30 V.

The FS drain efficiency η_drain takes into account the final stage only. Hence, η_drain cannot be measured directly because a part of the FS current flows into the high-side driver. As shown in Figs 2 and 5 (right) the drains of V2H and V3H are connected to the adjacent CT node, so that the final stage output feeds the positive rail of the high-side driver. Therefore, η_drain can be obtained only for simulations when one has access to all currents and voltages within the circuit.

From the η_tot characteristics (simulation and measurement) in Fig. 14 one clearly observes that the simulation using the EM simulation-based model of the coils matches the measured circuit quite well, particularly for maximum output power (0 dB PBO) and 10 dB back-off. A maximum difference of 6 percentage points (at 3 dB PBO) has been achieved between simulation and measurement. Considering this the simulated FS drain efficiency values given in Fig. 14 can be considered as realistic as well. This is important since they cannot be measured as stated before.

At the maximum output power of 5.8 W, overall efficiency η_tot reaches 59% and decreases down to 25% at 10 dB PBO. The simulated FS drain efficiency peaks at 71% (0 dB PBO), drops down to 62% at 7 dB, and reaches 67% at 10 dB PBO. Moreover, the final stage efficiency stays above 50% even down to 15 dB PBO. The η_tot curve shows the potential of the digital outphasing approach presented here. In terms of dynamic range, we reached output powers below 1 mW. This means the DOPA reaches at least a dynamic range of 40 dB.

But we have to state that the total efficiency drop with increased PBO is not satisfying since the simulated FS drain efficiency shows an almost constant behavior. Possible reasons for that are discussed in the following.