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Understanding stress gradients in microelectronic metallization

Published online by Cambridge University Press:  15 June 2012

Conal E. Murray*
Affiliation:
IBM T.J. Watson Research Center, Yorktown Heights, New York
E. Todd Ryan
Affiliation:
GLOBALFOUNDRIES, Albany Nanotech Center, Albany, New York
Paul R. Besser
Affiliation:
GLOBALFOUNDRIES, Sunnyvale, California
Christian Witt
Affiliation:
GLOBALFOUNDRIES, T.J. Watson Research Center, Yorktown Heights, New York
Jean L. Jordan-Sweet
Affiliation:
IBM T.J. Watson Research Center, Yorktown Heights, New York
Michael F. Toney
Affiliation:
Stanford Synchrotron Radiation Lightsource, Menlo Park, California
*
a) Author to whom correspondence should be addressed. Electronic mail: conal@us.ibm.com

Abstract

The manufacture of ultra-large scale integration technology can impose significant strain within the constituent metallization because of the mismatch in coefficients of thermal expansion between metallization and its surrounding environment. The resulting stress distributions can be large enough to induce voiding within Cu-based metallization, a key reliability issue that must be addressed. The interface between the Cu and overlying capping layers is a critical location associated with void formation. By combining conventional and glancing-incidence X-ray diffraction, depth-dependent stress distributions that develop in Cu films and patterned features are investigated. In situ annealing and as-deposited measurements reveal that strain gradients are created in capped Cu structures, where an increased in-plane tensile stress is generated near the Cu/cap interface. The interplay between plasticity in Cu and the constraint imposed by capping layers dictates the extent of the observed gradients. Cu films possessing caps deposited at temperatures where Cu experienced only elastic deformation did not exhibit depth-dependent stress distributions. However, all capped Cu samples exposed to temperatures that induce plastic behavior developed greater tensile stress at the Cu/cap interface than in the bulk Cu film after cooling, representing a clear concern for the mitigation of metallization voiding.

Information

Type
Technical Articles
Copyright
Copyright © International Centre for Diffraction Data 2012
Figure 0

Figure 1. (Color online) X-ray diffraction stress measurements in (a) conventional mode and (b) glancing-incidence geometry.

Figure 1

Figure 2. (Color online) Measured Cu (222) reflection peaks vs. sin2(ψ) for (a) SiCxNyHz-capped Cu film and (b) CoWP-capped film, where ψ is the tilt angle between the surface normal and the diffraction vector.

Figure 2

Figure 3. (Color online) Measured Cu (220) reflection peaks vs. incidence angle for (a) SiCxNyHz-capped Cu film and (b) CoWP-capped film. The dashed lines refer to extrapolated bulk in-plane values for the SiCxNyHz-capped and CoWP-capped Cu films, respectively, as shown in Figure 2.

Figure 3

Figure 4. (Color online) Comparison of in-plane stress values in capped Cu films in bulk and near-surface regions for a variety of capping schemes, where “t-SiCNH” refers to a SiCxNyHz cap possessing a residual tensile stress, “hybrid” refers to a CoWP/SiCxNyHz cap and “a-CoWP” refers to a CoWP-capped Cu film exposed to annealing for 5 min at 350 °C.

Figure 4

Figure 5. (Color online) In-plane stress measured in the bulk and near-surface regions using Cu (422) reflection of a SiCxNyHz-capped Cu film during (a) heating and (b) cooling. The dashed curve, corresponding to stress evolution from elastic CTE mismatch, is included for comparison.

Figure 5

Figure 6. (Color online) Triaxial stress state in 150-nm wide Cu interconnect/low-k dielectric patterned features in bulk and near-surface regions, where σ11 corresponds to stress along the interconnect, σ22 to stress transverse to the interconnect, and σ33 to stress in the out-of-plane direction.