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Comparing planning problem compilation approaches for quantum annealing

Published online by Cambridge University Press:  22 February 2017

Bryan O’Gorman
Affiliation:
QuAIL, NASA Ames Research Center, Moffett Field, CA, USA; e-mail: bryan.a.ogorman@nasa.gov, eleanor.rieffel@nasa.gov Stinger Ghaffarian Technologies, Inc. 7701 Greenbelt Road, Suite 400 Greenbelt, MD 20770, USA; e-mail: minh.do@nasa.gov
Eleanor Gilbert Rieffel
Affiliation:
QuAIL, NASA Ames Research Center, Moffett Field, CA, USA; e-mail: bryan.a.ogorman@nasa.gov, eleanor.rieffel@nasa.gov
Minh Do
Affiliation:
Intelligent Systems Division, NASA Ames Research Center, Moffett Field, CA, USA; e-mail: jeremy.d.frank@nasa.gov Stinger Ghaffarian Technologies, Inc. 7701 Greenbelt Road, Suite 400 Greenbelt, MD 20770, USA; e-mail: minh.do@nasa.gov
Davide Venturelli
Affiliation:
QuAIL, NASA Ames Research Center, Moffett Field, CA, USA; e-mail: bryan.a.ogorman@nasa.gov, eleanor.rieffel@nasa.gov Universities Space Research Association 615 National Avenue, Suite 220 Mountain View, CA 94043, USA; e-mail: davide.venturelli@nasa.gov
Jeremy Frank
Affiliation:
Intelligent Systems Division, NASA Ames Research Center, Moffett Field, CA, USA; e-mail: jeremy.d.frank@nasa.gov
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Abstract

One approach to solving planning problems is to compile them to other problems for which powerful off-the-shelf solvers are available; common targets include SAT, CSP, and MILP. Recently, a novel optimization technique has become available: quantum annealing (QA). QA takes as input problem instances of quadratic unconstrained binary optimization (QUBO) problem. Early quantum annealers are now available, though their constraints restrict the types of QUBOs they can take as input. Here, we introduce the planning community to the key steps in compiling planning problems to QA hardware: a hardware-independent step, mapping, and a hardware-dependent step, embedding. After describing two approaches to mapping general planning problems to QUBO, we describe preliminary results from running an early quantum annealer on a parametrized family of hard planning problems. The results show that different mappings can substantially affect performance, even when many features of the resulting instances are similar. We conclude with insights gained from this early study that suggest directions for future work.

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Type
Articles
Copyright
© Cambridge University Press, 2017 
Figure 0

Figure 1 (Left) The main steps in using quantum annealer to solve an application problem. (Right) A schematic diagram from Smelyanskiy et al., (2012) of the (M, L)-Chimera graph underlying D-Wave’s architecture. In the (3, 4)-Chimera graph shown, there are M2=9 unit cells, each of which is a fully-connected bipartite graph K4,4 containing 2L qubits

Figure 1

Figure 2 Comparison of the median expected total anneal time to 99% success for the two mappings. Each data point shows the median expected total annealing time to achieve 99% success over the 100 problems of each size given on the x-axis. The error bars are at the 35th and 65th percentiles. When at least half of the instances do not solve within the 0.9 seconds effective cutoff time, we no longer show the point. Also, when fewer than 65% solve, the top of the error bar is indeterminate, as happened for the last point shown in both the conjunctive normal form (CNF) and time-slice (TS) series

Figure 2

Figure 3 Analysis and comparison of mapped and embedded Quadratic Unconstrained Binary Optimization (QUBO) features for each problem size under three mappings: direct mapping, time-slice mapping, and conjunctive normal form (CNF) mapping (a) Vertex degree histogram. Histograms of the vertex degrees for the mapped QUBO graphs. (b) Vertex model size histogram. Histograms of the vertex model sizes in the embedded QUBOs. (c) QUBO coefficient histogram. Histograms of the hi and Jij in the mapped QUBOs. (d) Histogram of hi and ji=ΣjJij. Histograms of the hi and ji=ΣjJij in the mapped QUBOs.