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Compact RF non-linear electro thermal model of SiGe HBT for the design of broadband ADC's

Published online by Cambridge University Press:  29 August 2012

Alaa Saleh*
Affiliation:
XLIM – CNRS 123, Avenue Albert Thomas, 87060 Limoges Cedex, France
Abdel Kader El Rafei
Affiliation:
XLIM – CNRS 123, Avenue Albert Thomas, 87060 Limoges Cedex, France
Mountakha Dieng
Affiliation:
XLIM – CNRS 123, Avenue Albert Thomas, 87060 Limoges Cedex, France
Tibault Reveyrand
Affiliation:
XLIM – CNRS 123, Avenue Albert Thomas, 87060 Limoges Cedex, France
Raphael Sommet
Affiliation:
XLIM – CNRS 123, Avenue Albert Thomas, 87060 Limoges Cedex, France
Jean-Michel Nebus
Affiliation:
XLIM – CNRS 123, Avenue Albert Thomas, 87060 Limoges Cedex, France
Raymond Quere
Affiliation:
XLIM – CNRS 123, Avenue Albert Thomas, 87060 Limoges Cedex, France
*
Corresponding author: Alaa Saleh Email: salehalaa83@gmail.com
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Abstract

The design of high speed integrated circuits heavily relies on circuit simulation and requires compact transistor models. This paper presents a non-linear electro-thermal model of SiGe heterojunction-bipolar transistor (HBT). The non-linear model presented in this paper uses a hybrid π topology and it is extracted using IV and S-parameter measurements. The thermal sub-circuit is extracted using low-frequency S-parameter measurements. The model extraction procedure is described in detail. It is applied here to the modeling of npn SiGe HBTs. The proposed non-linear electro-thermal model is expected to be used for the design of high-speed electronic functions such as broadband analog digital converters in which both electrical and thermal aspects are engaged. The main focus and contribution of this paper stands in the fact that the proposed non-linear model covers wideband-frequency range (up to 65 GHz).

Information

Type
Research Papers
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2012
Figure 0

Fig. 1. Model topology.

Figure 1

Fig. 2. DC IV measurements of a 3 × 2.8 × 0.35 µm2 SiGe HBT.

Figure 2

Fig. 3. Current gain versus collector current measured at Vce = 1 V.

Figure 3

Fig. 4. Simulated IV network with constant current gain (a) and variable current gain versus collector current (b). (Ib_start 1 µA; Ib_step: 40 µA; and Ib_stop: 201 µA).

Figure 4

Fig. 5. Simulated and measured IV network with breakdown modeling. (Ib_start = 1 µA; Ib_step = 40 µA; and Ib_stop = 201 µA).

Figure 5

Fig. 6. Transition frequency versus collector current.

Figure 6

Fig. 7. Transition frequency versus collector emitter voltage.

Figure 7

Fig. 8. Simulated and measured Ic versus Vce for different chuck temperature.

Figure 8

Fig. 9. (a) Imaginary part of thermal impedance. (b) Real part of thermal impedance.

Figure 9

Fig. 10. Enhanced thermal sub circuit description.

Figure 10

Table 1. Scaling rules of model parameters X_u denotes the value of the parameter X for AE = 2.94 µm2 (emitter area for the smallest transistor 3 × 2.8 × 0.35 µm2).

Figure 11

Fig. 11. Simulated and measured IV network (Ib_start = 1 µA; Ib_step = 50 µA; and Ib_stop = 301 µA).

Figure 12

Fig. 12. (a) Measured versus simulated S11. (b) Measured versus simulated S21.(c) Measured versus simulated S12. (d) Measured versus simulated S22.

Figure 13

Fig. 13. Measured and simulated gain versus input power.

Figure 14

Fig. 14. Simulated and measured   waveforms (Vbe = 0.8 V, Vce = 1.2 V, and input power = −20 dBm). (a) Collector emitter voltage. (b) Collector current. (c) Base emitter voltage. (d) Base current.

Figure 15

Fig. 15. Simulated and measured DC collector current.

Figure 16

Fig. 16. Measured and simulated gain versus input power.

Figure 17

Fig. 17. Simulated and measured   waveforms (Vbe = 0.8 V, Vce = 1.2 V, and input power = −20 dBm). (a) Collector emitter voltage. (b) Collector current. (c) Base emitter voltage. (d) Base current.

Figure 18

Fig. 18. Simulated and measured DC collector current.