Hostname: page-component-74656f9884-c52kr Total loading time: 0 Render date: 2026-11-08T08:03:38.027Z Has data issue: false hasContentIssue false

Modified High-Resolution Correlator Technique for Short-Delayed Multipath Mitigation

Published online by Cambridge University Press:  15 June 2009

Hyoungmin So*
Affiliation:
(Seoul National University)
Ghangho Kim
Affiliation:
(Seoul National University)
Taikjin Lee
Affiliation:
(Seoul National University)
Sanghoon Jeon
Affiliation:
(Seoul National University)
Changdon Kee
Affiliation:
(Seoul National University)
*
Rights & Permissions [Opens in a new window]

Abstract

Multipath is one of the main error sources in global navigation satellite system (GNSS) positioning. The high-resolution correlator (HRC) is a multipath mitigation technique well known for its outstanding performance for mid-delayed multipath, but still has a remaining error for the short-delayed multipath. This paper proposes a modified HRC scheme that can remove or reduce the error for short-delayed multipath signals. It estimates the HRC tracking error and augments the conventional HRC with the estimates. The method was implemented with a software receiver and the test results show short-delayed multipath-induced errors were reduced to about one third of those from the conventional HRC.

Information

Type
Research Article
Copyright
Copyright © The Royal Institute of Navigation 2009
Figure 0

Figure 1. Auto-correlation function (ACF) and construction of HRC.

Figure 1

Figure 2. Multipath error envelopes of EML, narrow correlator and HRC.

Figure 2

Figure 3. Geometry of ACF and HRC tracking status for in-phase multipath.

Figure 3

Figure 4. Geometry of ACF- and HRC-tracking status for out-of-phase multipath.

Figure 4

Figure 5. ACF with LOS and in-phase multipath signals (left) and ACF with LOS and out-of-phase multipath ones (right).

Figure 5

Figure 6. Geometry of ACF and HRC operation for in-phase multipath when the HRC works well for mid-delayed multipath (left) and it could not work for short-delayed one (right).

Figure 6

Figure 7. Parameters of HRC correlators when in-phase multipath is induced.

Figure 7

Figure 8. Geometry of ACF and HRC operation for out-of-phase multipath when the HRC works well for mid-delayed multipath (left) and it could not work for short-delayed one (right).

Figure 8

Figure 9. Parameters of HRC correlators when in-phase multipath is induced.

Figure 9

Figure 10. In-phase and out-of-phase multipath decision parameter 1 and 2.

Figure 10

Figure 11. Simulated error envelope of modified HRC (left) and an enlarged plot for short delay below 0·2 chip (right).

Figure 11

Figure 12. Simulated error envelope of modified HRC with 24 MHz bandwidth (left) and an enlarged plot for short delay below 0·2 chip (right).

Figure 12

Figure 13. Simulated error envelope of modified HRC with 12 MHz bandwidth (left) and an enlarged plot for short delay below 0·2 chip (right).

Figure 13

Figure 14. Simulated error envelope of modified HRC using parameter 1 only (left) and an enlarged plot for short delay below 0·2 chip (right).

Figure 14

Figure 15. Simulated error envelope of modified HRC with 24 MHz bandwidth using parameter 1 only (left) and an enlarged plot for short delay below 0·2 chip (right).

Figure 15

Figure 16. Simulated error envelope of modified HRC with 12 MHz bandwidth using parameter 1 only (left) and an enlarged plot for short delay below 0·2 chip (right).

Figure 16

Figure 17. Fixed 0·05 chip delayed in-phase multipath, code discriminator output (left), tracking error (middle) and tracked signal power (right).

Figure 17

Figure 18. Fixed 0·1 chip delayed in-phase multipath, code discriminator output (left), tracking error (middle) and tracked signal power (right).

Figure 18

Figure 19. Fixed 0·15 chip delayed in-phase multipath, code discriminator output (left), tracking error (middle) and tracked signal power (right).

Figure 19

Figure 20. Fixed 0·2 chip delayed in-phase multipath, code discriminator output (left), tracking error (middle) and tracked signal power (right).

Figure 20

Figure 21. Linearly varying delayed multipath from 0 to 0·3 chip during 60 seconds, code discriminator output (left), tracking error (middle) and tracked signal power (right).