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An L-band SiGe HBT differential amplifier with frequency and rejection-level tunable, multiple stopband

Published online by Cambridge University Press:  22 June 2009

Masaki Shirata
Affiliation:
Department of Electrical and Electronic Engineering, Shonan Institute of Technology, 1-1-25 Tsujido-Nishikaigan, Fujisawa, Kanagawa 251-8511Japan. Phone & Fax: +81-466-30-0185.
Toshio Shinohara
Affiliation:
Department of Electrical and Electronic Engineering, Shonan Institute of Technology, 1-1-25 Tsujido-Nishikaigan, Fujisawa, Kanagawa 251-8511Japan. Phone & Fax: +81-466-30-0185.
Minoru Sato
Affiliation:
Department of Electrical and Electronic Engineering, Shonan Institute of Technology, 1-1-25 Tsujido-Nishikaigan, Fujisawa, Kanagawa 251-8511Japan. Phone & Fax: +81-466-30-0185.
Yasushi Itoh*
Affiliation:
Department of Electrical and Electronic Engineering, Shonan Institute of Technology, 1-1-25 Tsujido-Nishikaigan, Fujisawa, Kanagawa 251-8511Japan. Phone & Fax: +81-466-30-0185.
*
Corresponding author: Y. Itoh E-mail: itohy@center.shonan-it.ac.jp
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Abstract

An L-band frequency and rejection-level tunable SiGe HBT differential amplifier with dual stopband is presented. To achieve frequency and rejection-level tunable performance, dual LCR-tank circuit with an active load is incorporated into the design of the series feedback loops of the differential amplifier. The active load consists of a varactor diode represented as a variable C and a common-emitter transistor represented as a variable R. The frequency and rejection level can be tuned independently by controlling a cathode bias voltage of the varactor diode or a base bias voltage of the transistor. The implemented 0.35 μm SiGe HBT amplifier with dual stopband demonstrates a frequency tuning of 0.53–1.16 GHz and a rejection-level variation up to 9.5 dB. The input and output return losses are better than 17.5 and 11 dB over 0.2–1.5 GHz, respectively. The measured P1dB is+3 dBm and IIP3 is 0 dBm with Vcc = 6 V and Ic = 8 mA.

Information

Type
Original Article
Copyright
Copyright © Cambridge University Press and the European Microwave Association 2009
Figure 0

Fig. 1. Schematic diagram of the frequency and rejection-level tunable differential amplifier with dual stopband.

Figure 1

Fig. 2. Simplified schematic diagram of Fig. 1.

Figure 2

Fig. 3. Gain and rejection peaks of the amplifier.

Figure 3

Fig. 4. Simulated gain and return loss of the frequency and rejection-level tunable differential amplifier with dual stopband.

Figure 4

Fig. 5. Photograph of the frequency and rejection-level tunable differential amplifier with dual stopband.

Figure 5

Fig. 6. Measured gain and return loss of the frequency-tunable, dual-stopband differential amplifier.

Figure 6

Fig. 7. Measured gain for a varied value of Vc1 and a fixed value of Vc2.

Figure 7

Fig. 8. Measured input return loss for a varied value of Vc1 and a fixed value of Vc2.

Figure 8

Fig. 9. Measured output return loss for a varied value of Vc1 and a fixed value of Vc2.

Figure 9

Fig. 10. Measured gain for a varied value of Vc2 and a fixed value of Vc1.

Figure 10

Fig. 11. Measured input return loss for a varied value of Vc2 and a fixed value of Vc1.

Figure 11

Fig. 12. Measured output return loss for a varied value of Vc2 and a fixed value of Vc1.

Figure 12

Fig. 13. Calculated K-factor for a varied value of f1 and a fixed value of f2.

Figure 13

Fig. 14. I–V characteristics of the transistor.

Figure 14

Fig. 15. Measured gain for a varied value of Vc3 and a fixed value of Vc4.

Figure 15

Fig. 16. Measured gain for a varied value of Vc4 and a fixed value of Vc3.

Figure 16

Fig. 17. Variation of the number of stopband with the control of Vc1 and Vc2.

Figure 17

Fig. 18. Measured noise figure performance of the lossy match and reactive match amplifiers.

Figure 18

Fig. 19. Schematic diagram of the lossy match and reactive match configurations.

Figure 19

Fig. 20. Schematic diagram of the lossy match and negative feedback configurations.

Figure 20

Fig. 21. Measured gain and IIP3 with a parameter of RF for the negative feedback configuration.

Figure 21

Fig. 22. Measured IIP3 with a parameter of IC.