A) Variation of load and source impedances at f ₀ and 2f ₀

Variation of the fundamental or harmonic frequency impedance can be carried out passively by means of a tuner or actively by injecting a power wave toward the transistor [Reference Deshours, Bergeault, Jallet and Huyart14–Reference Ferrero and Pisani17]. In the proposed setup, source-pull/load-pull measurements at fundamental and harmonic frequencies are performed using an active loop architecture. Thus, the setup is composed of four active loops: two at the source side (at f ₀ and 2f ₀) and two at the load side (at f ₀ and 2f ₀). Source impedances at f ₀ and 2f ₀ are controlled independently by means of the broadband circulator Cir₁ and the band-pass filters BPF₁ and BPF₂. The same configuration is used at the DUT output termination with the circulator Cir₂ associated with the band-pass filters BPF₃ and BPF₄. Each active loop is associated with a six-port reflectometer used as an automatic network analyzer that allows the measurement of the reflection coefficient of the source impedances Γ_S(f ₀) and Γ_S(2f ₀) (by six-ports 1 and 4, respectively) [Reference Bergeault, Gibrat, Bensmida and Huyart18], the reflection coefficient of the load impedances Γ_L(f ₀) and Γ_L(2f ₀) (by six-ports 2 and 3, respectively), and finally the DUT input reflection coefficient Γ_in(f ₀) (by six-port 1). This solution is attractive as very low-cost six-port reflectometers can be implemented in microstrip technology. An active loop (which is detailed in Fig. 1 and used for fundamental source impedance control) includes a high-gain power amplifier A ₂, a phase shifter, and a variable attenuator. Consequently, high values for the magnitude of the source reflection coefficient can be synthesized at the DUT plan. A reconfigurable yttrium iron garnet (YIG) filter is used to avoid loop oscillations and is set to be centered at the loop frequency of operation. Depending on the position of the switch SW₁, the six-port reflectometers 1 and 4 measure either the input reflection coefficients of the DUT Γ_in(f ₀) and Γ_in(2f ₀) (SW₁ in position 2) or the reflection coefficient presented to its input Γ_S(f ₀) and Γ_S(2f ₀) (SW₁ in position 1). A simple one-step calibration procedure is required as the calibration constants of the six-port reflectometer are independent of SW₁ position.

B) Low-frequency impedances optimization

Low-frequency load impedances Z _LLF are synthesized at the signal envelop frequency (equal to 1 MHz for the measurement results reported in this paper) using an electronically controlled passive tuner realized with resistors, capacitors, and inductors. In order to achieve independent control of RF and low-frequency impedances, two different bias tees are combined at the output of the DUT: high-frequency bias tee BT₂ (0.8–4 GHz) associated with low-frequency bias tee BT₄ (10 kHz–12 GHz). Similarly, the low-frequency source impedance Z _SLF can also affect transistor linearity. Consequently, the same configuration is used for base-band impedance control at the DUT input. The electrical delay of these terminations must be minimized to avoid variation of the reflection coefficient within the bandwidth of the modulated signal. The total phase shift of the base-band reflection coefficient is about 8°/MHz. The bandwidth of the test signal is actually limited to 5 MHz but a wider bandwidth can be achieved with six-port diode detectors showing lower values of the video resistance [Reference Abou Chakra and Huyart19].

C) Base-band predistortion linearization technique

An instantaneous memoryless polynomial base-band predistortion is deduced from the measurements of AM/PM and AM/AM characteristics. The complete description of the base-band predistortion method is reported in [Reference Abib, Bensmida, Bergeault and Huyart12]. AM/PM conversion is measured by a digital oscilloscope, whereas instantaneous AM/AM conversion is obtained by means of two fast zero-bias Schottky diodes D ₁ and D ₂ followed by a data acquisition card. Diode detectors operate only in the square law region at low power levels. In order to achieve accurate measurements over a wide power dynamic range, a linearization procedure of the diodes is applied according to the method described in [Reference Bergeault, Huyart, Geneves and Jallet20]. Adjacent channel power ratio (ACPR) and error vector magnitude (EVM) measurements are performed using a spectrum/signal analyzer connected at the output of the DUT. The original and corrected base-band signals are stored in the arbitrary waveform generator of the RF vector signal generator. The different steps for the calibration of the measurement system are the following:

• • Calibration of the six-port reflectometers (measurement of power levels Pin and Pout, reflection coefficients of the DUT, and source/load reflection coefficients) using the method described in [Reference Bensmida, Bergeault, Abib and Huyart10].

• • Linearization of the fast zero-bias Schottky diodes [Reference Bergeault, Huyart, Geneves and Jallet20] (measurement of AM/AM).

A) Source-pull/load-pull measurements at f ₀ and 2f ₀

Initial values for fundamental and harmonic source and load impedances are equal to 50 Ω. The first optimization concerns the determination of the fundamental load impedance that optimizes Pout (f ₀) and PAE. The optimum load reflection coefficient Γ_L(f ₀) = 0.4∠128°, obtained from load-pull measurements, increases output power from 26 to 28 dBm. At the same time, PAE is increased from 37 to 53%. Then a complete source-pull characterization is performed at f ₀. Both ACPR and EVM are measured as well as gain mismatch at the input, i.e. when Γ_S = Γ_in*. Depending on the value of the source reflection coefficient, variations of 3 dB, 5 dB, 1 percentage point, and 10 dB are observed for ACPR, ACPR asymmetry, EVM, and input gain mismatch, respectively. The conjugate matched source impedance is in the instable zone and could lead to oscillations of the transistor. Consequently, in this region, the magnitude of the source reflection coefficient is limited to 0.8. Figure 2(a) shows the locations of the optimum source impedances obtained for gain mismatch and linearity. Moreover, source-pull contours for gain mismatch are also plotted. Figure 2(b) shows the fundamental source-pull contours for ACPR. The measurement results show that the fundamental source impedance Z_S(f ₀) has a significant effect on linearity. Linearity is degraded when the source impedance varies from 50 Ω (optimum linearity) to a conjugate match (optimum input gain mismatch). These observations are in agreement with those reported in [Reference Liu, Dunleavy and Arslan1] on an L-band high-power GaAs FET device. Consequently, a trade-off between input gain mismatch and linearity has to be found. For a source reflection coefficient Γ_S(f ₀) = 0.26∠144°, ACPR and EVM are close to their optimum values (Table 1). On the other hand, this trade-off impedance decreases the optimum stable mismatch gain by 3 dB but, compared to the worst case, improves ACPR and EVM by 2.3 dB and 0.4 point, respectively.

Fig. 2.

Source-pull contours at f ₀ for (a) gain mismatch and (b) ACPR.

Table 1.

Effects of source impedance at f ₀.

For the load-pull measurements at 2f ₀, no optimal impedances for output power, PAE, and linearity at the same time were found. Thus, we decided to set |Γ_L(2f ₀)| to 0.9 and the phase φ of Γ_L(2f ₀) was swept from 0 to 360°. Figures 3(a) and 3(b) show ACPR, Pout(f ₀), and EVM, PAE versus φ(Γ_L(2f ₀)), respectively. We notice that Z _L(2f ₀) has an important influence on ACPR and EVM, leading to variations equal to 9 dB and 3 points, respectively. Unfortunately, when linearity increases, Pout and PAE decrease and vice versa. Therefore, Z _L(2f ₀) is chosen to be set to 50 Ω. The same measurement procedure was performed with the source impedance at 2f ₀. |Γ_S(2f ₀)| was set to 0.9 and the phase φ of Γ_S(2f ₀) was swept from 0 to 360°. Figures 4(a) and 4(b) show ACPR, Pout(f ₀), and EVM, PAE versus φ(Γ_S(2f ₀)), respectively. As observed previously, when linearity increases (4 dB variations for ACPR), Pout and PAE decrease and vice versa. Unlike the load impedance, the source impedance at the second harmonic improves the linearity when φ(Γ_S(2f ₀)) = 270°. This impedance, compared to the worst and 50 Ω cases, improves the ACPR by 3 and 1.5 dB, respectively, whereas the output power and efficiency are maintained at their optimal values (Pout = 28 dBm and PAE = 52%). We have also retuned the load-pull at f ₀ after optimizing the second harmonic load. For this transistor, the optimum load at the fundamental frequency remains unchanged. Of course, this would not be the case depending on the DUT. All these results show the usefulness of the harmonic source and load-pull characterizations. If there are no optimal impedances, at least performance degradation can be avoided.

Fig. 3.

(A) ACPR and Pout versus φ, and (B) EVM and PAE versus φ when |Γ_L(2f ₀)| = 0.9 and φ(Γ_L(2f ₀)) is variable.

Fig. 4.

(A) ACPR and Pout versus φ, and (B) EVM and PAE versus φ when |Γ_S(2f ₀)| = 0.9 and φ(Γ_S(2f ₀)) is variable.

B) Low-frequency impedances optimization

The load and source reflection coefficients at the fundamental frequency are now fixed to 0.4∠128° and 0.26∠144°, respectively. At 2f ₀, Γ_L(2f ₀) = 0 and Γ_S(2f ₀) = 0.9∠270°. Figures 5(a) and 5(b) show the large influence of low-frequency load impedances Z _LLF on transistor linearity (ACPR and EVM versus Pout, respectively) over a wide output power range. As expected, the optimum impedance is close to a short circuit while an open circuit significantly reduces the device linearity. However, it is important to measure the influence of Z _LLF because compensation of electrical, thermal, and trap effects can lead to an optimum complex value [Reference Sevic, Burger and Steer8, Reference Bensmida, Bergeault, Abib and Huyart10]. Depending on the base-band impedance, maximum ACPR and EVM variations are found to be 15 dB and 5.5 points, respectively. One observes maximum ACPR close to the compression point for an output power equal to 26 dBm due to the gain expansion phenomena. Therefore, the control of this impedance presents a significant potential advantage since the highest linearity can be achieved at a substantially improved efficiency and output power (Pout = 28 dBm, PAE = 52%, ACPR and EVM improvements equal to 10 dB and 5.5 points, respectively). On the other hand, no significant influence of low-frequency source impedances Z _SLF has been observed for this transistor, but this would not be the case for strongly non-linear transistors like HBT for example [Reference Williams, Leckey and Tasker7].

Fig. 5.

(A) ACPR versus Pout, and (B) EVM versus Pout for different low-frequency load impedances Z _LLF.

C) Base-band predistortion linearization technique

Fundamental and low-frequency terminations are fixed to previously determined values. Transistor linearity can still be improved by applying instantaneous memoryless base-band predistortion using the same setup. Figures 6(a) and 6(b) show the ACPR and EVM values versus Pout, with and without predistortion. The linearization procedure does not have a significant effect in the linear region. Otherwise, in the compression region, improvements of 5 dB and 1 percentage point are observed for ACPR and EVM, respectively. Predistortion can be applied up to a limit value equal to 28.5 dBm corresponding to the saturation of transistor for which the memoryless linearization procedure is no longer efficient.

Fig. 6.

(A) ACPR versus Pout, and (B) EVM versus Pout with and without linearization.