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An ultra-wideband power amplifier designed through a bandwidth expansion strategy

Published online by Cambridge University Press:  13 May 2024

Xuefei Xuan*
Affiliation:
The School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, China The School of Electronic Engineering, Huainan Normal University, Huainan, China The School of Electronic Engineering, Dublin City University, Dublin, Ireland
Zhiqun Cheng
Affiliation:
The School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, China The School of Information Engineering, Xinjiang Institute of Technology, Xinjiang, China
Brendan Hayes
Affiliation:
The School of Electronic Engineering, Dublin City University, Dublin, Ireland
Zhiwei Zhang
Affiliation:
The School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, China
Tingwei Gong
Affiliation:
The School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, China
Shenbing Wu
Affiliation:
The School of Electronic Engineering, Huainan Normal University, Huainan, China
Chao Le
Affiliation:
The School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, China
*
Corresponding author: Xuefei Xuan; Email: xuanxuefei2022@163.com
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Abstract

A bandwidth expansion strategy for ultra-wideband power amplifiers (PAs) is presented in this letter by adopting a parallel impedance matching architecture. This design strategy can effectively reduce the impedance conversion ratio between the load and the target impedance of the PA, thereby providing a feasible solution for broadband impedance matching. Subsequently, a commercially available 10 W gallium nitride device and a two-stage Wilkinson power divider network are combined to achieve the verification of the proposed theory. The results of the measurement show that within the target frequency band of 0.9–3.9 GHz, 58.5–71.2% of the drain efficiency and 9.1–12 dB of gain can be achieved with a saturated output power of 39.1–42 dBm.

Information

Type
Research Paper
Copyright
© The Author(s), 2024. Published by Cambridge University Press in association with The European Microwave Association.
Figure 0

Figure 1. Schematic diagram of proposed parallel impedance matching architecture.

Figure 1

Figure 2. Optimal impedances distribution for load in 1.0–4.0 GHz.

Figure 2

Figure 3. Schematic of the designed PA. Dimensions are in mm.

Figure 3

Figure 4. Impedance trajectory completed by output matching network.

Figure 4

Figure 5. Fabricated PA circuit.

Figure 5

Figure 6. Measured and simulated DE, output power, and gain (at saturation) vs. frequency.

Figure 6

Table 1. Comparisons with state-of-the-art broadband PAs

Figure 7

Figure 7. Measured DE and gain vs. output power for some in-band frequencies.