II. DESIGN AND MODELING

A simplified schematic of the proposed 2-way in-phase equal power divider is shown in Fig. 1(b). Compared with the conventional 2-way Wilkinson divider (Fig. 1(a)), the new divider comprises of four quarter-wave transmission lines, a phase inverter, two lumped resistors, and three ports. The transitions from the transmission lines to the ports are represented as ideal transformers. To be compatible with MMICs, a hybrid coplanar design using symmetric CPSs as the main body of the divider and CPWs as ports is selected. The waveguides are finally configured in a ring structure as shown in Fig. 2.

Fig. 2.

The proposed hybrid power divider is configured in a ring structure.

Similar to the Wilkinson divider, the characteristic impedance, Z _0cps, of the quarter-wave length CPSs between the input port (Port 1) and the output ports (Port 2 and Port 3) is equal to $\sqrt{2}\; Z_0$ for optimum transmission and matching at the input port. This can be derived using the well-known even-odd mode method [Reference Pozar14]. Z ₀ is the system impedance that is 50 Ω in most cases. The additional two quarter-wave length CPSs between the two output ports also have the same characteristic impedance of $\sqrt{2}\; Z_0$. A crossover joins the two parts and forms a frequency-insensitive phase inverter. The combination of phase inverter, the two quarter-wave length transmission lines and two lumped resistors (R = 2Z ₀) allows almost full-band isolation between the two output ports. The schematic (Fig. 1(b)) was simulated using Agilent ADS Schematic and its ideal S-parameters are plotted in Fig. 1(c) against those of a Wilkinson divider. One can see that the new divider shows excellent bandwidth and isolation performance.

As a design guide for a practical coplanar hybrid power divider such as the one shown in Fig. 2, the characteristic impedances of CPWs and CPSs are derived using the following equations or the charts given in [Reference Ghione and Nald15].

(1)$$Z_{0CPW} = \displaystyle{30\pi \over \sqrt{\varepsilon_{eff}}} {K\left(k^{\prime} \right)\over K\left(k \right)}\comma \;$$

(2)$$Z_{0CPS} = \displaystyle{120\pi \over \sqrt{\varepsilon_{eff}}} \displaystyle{K\left(k \right)\over K\left(k^{\prime} \right)}\comma$$

(3)$$\varepsilon_{eff} = 1 + \displaystyle{\varepsilon_r - 1 \over 2} \displaystyle{K\left(k^{\prime} \right)K\left(k_1 \right)\over K\left(k \right)K\left(k^{\prime}_1 \right)}\comma$$

(4)$$k=\displaystyle{a \over b}\comma$$

(5)$$k_1 = \displaystyle{sinh \left({\pi a \over 2h} \right)\over sinh \left({\pi b \over 2h} \right)}\comma$$

where a and b are defined as W _CPW /2 and S _CPW + W _CPW /2 for CPWs and S _CPS /2 and S _CPW + W _CPW /2 are for CPS, respectively. W _cpw and S _cpw are the central conductor width and the gap between the central conductor and the ground conductor of the CPWs. W _cps and S _cps are the conductor width and gap between the conductors of the symmetric CPS. ɛ _r and h are the dielectric constant and height of the substrate, respectively. According to the design charts given in [Reference Ghione and Nald15] and equations (1–5), a characteristic impedance of 50 Ω CPW on a 620 µm thick semi-insulating GaAs substrate, which has a relative dielectric constant of 12.9, requires the ratio of W _cpw to S _cpw to be approximately 1.3. At lower millimeter-wave frequency range (<50 GHz) they are 60 and 40 µm while at higher millimeter-wave frequencies (up to 220 GHz) they are normally chosen to be 20 and 15 µm for better field confinement [Reference Lok, Hwang, Chong, Elgaid and Thayne16]. Similarly, the characteristic impedance of a symmetric CPS, Z _0cps, is 70.7 Ω and requires an approximate ratio of W _cps to S _cps to be 0.3. In order to compromise W _cpw, W _cps was chosen to be the same as W _cpw. This leads to an S _cps value of 24 and 8 µm at below and above 50 GHz, respectively. Once W _cps and S _cps are finalized, the corresponding effective dielectric constant, ɛ _eff, of the CPS can be derived from equations (3–5) therefore the wavelength at the center design frequency uses the following equation

(6)$$\lambda_g = {\lambda \over \sqrt{\varepsilon_{eff}}}\comma$$

where λ is the wavelength of the center design frequency in vacuum. Definitions and values of all parameters for the center design frequencies of 25 and 80 GHz are listed in Table 1.

Table 1.

Parameters and values of the proposed power dividers at the center frequencies of 25 GHz and 80 GHz.

The length of the crossover, L _CO, or alternatively the length of resistors, L _R, is optimized using ADS Momentum for investigation of extra insertion loss. Two simulation setups for an 80 GHz divider were carried out: one with a half-wave length CPS and two differential ports excited at two ends; the other one has two quasi quarter-wave lengths CPS that are joined at the elevated crossover. Similarly, both ports were set at the sides and assigned an impedance of 70.7 Ω. The gap between the two sections of CPS varied from 15 to 30 µm by steps of 5 µm, the extra insertion loss, which is the difference between the insertion loss of the crossover and that of the CPS, is shown in Fig. 3(a). It can be seen that the 20 µm gap that corresponds to crossover of approximately 30 µm gives the lowest extra insertion loss.

Fig. 3.

Extra insertion loss for (a) different gap lengths between two sections of CPS varying from 15 to 30 µm by steps of 5 µm and (b) variation of crossover height from 1 to 6 µm by steps of 1 µm.

The height of the crossover, H _ab, also affects the insertion loss of the crossover. With all other parameters fixed, by changing H _ab from 1 to 6 µm in steps of 1 µm, the extra insertion loss increases at the center operating frequency of 80 GHz as shown in Fig. 3(b). It indicates that lower the crossover height lower the extra insertion loss of the crossover. A higher crossover requires extra height of crossover posts which introduces additional parasitic inductance, therefore extra loss is induced. This performance is better than that of the via-based phase inverter implementation [Reference Chiu and Xue3] due to its smaller parasitic inductance from the crossover posts. However, it becomes complicated when taking the entire power divider into account. This is because the height of the crossover is also the height of the airbridges that connect the two ground planes of CPWs at three ports to suppress any unwanted modes or to level the potentials. Lower airbridges lead to higher parasitic capacitance, therefore higher characteristic impedance, greater mismatch, and consequently reduced transmission. In addition, lower airbridges may be difficult to achieve from a fabrication point of view. Thus, to obtain the optimum height of crossover and airbridges, a balance has to be met. Three-dimensional (3D) full-wave simulations were performed to investigate these geometric parameters and their effects on power divider performance; however, due to the page limit detailed results are not presented here. However, the final simulation results from the divider with a H _ab of 4 µm are shown in Figs 4 and 5.

Fig. 4.

Simulated S-parameters of the proposed power divider at the center frequency of 80 GHz.

Fig. 5.

Simulated (a) variation of output port isolations and (b) output port match (Port 2) for different resistor values (in 20 Ω steps) of the 80 GHz divider.

Regarding the formation of two lumped resistors, the common method in MMIC technology is depositing conducting thin-film dielectrics or metal alloys onto a substrate. The length, L _R, to width, W _R, ratio determines the resistance once the sheet resistance of the material is known. We used an NiCr thin film due to its availability in our cleanroom facility. A 33 nm thick NiCr film gives a sheet resistance of 50 Ω/Square that is equivalent to a bulk conductivity of 606 100 S/m. Thus, a 100 Ω resistor requires the length to width ratio to be 2. The dimensions of the lumped resistors were chosen to be 20 µm × 10 µm for the 80 GHz divider.

The final divider was simulated using a 3D full-wave electromagnetic modeling tool Ansoft HFSS™. Lumped ports with an impedance of 50 Ω were used as port excitations. In order to avoid interference with surrounding circuits and to get better port isolation, NiCr resistors have also been applied between the three ports. The simulated surface current flows at phases of 0° and 90° at the center frequency of 80 GHz are shown in Fig. 6 when the port excitation was assigned onto Port 3 (left port). One can see clear evidence of current flow from Port 3 to Port 1 (top port) but negligible current flowing between Port 2 and Port 3 at both 0° phase (Fig. 6(a)) and 90° phase. The S-parameters magnitudes (dB) of the proposed 80 GHz power dividers are plotted in Fig. 4. It is clearly seen that the port isolation (|S₃₂|) is better than 17 dB across the entire simulated frequency band (10–160 GHz). The port return losses (|S₁₁| and|S₂₂|) are better than 15 dB over the frequency range from 44 to 112 GHz. Return loss at Port 3 that is approximately identical to Port 2 is not shown here.

Fig. 6.

Simulated surface current flows at two different phases (a) 0° and (b) 90° of the proposed power divider at 80 GHz when the port excitation was from Port 3.

Although extreme care must be taken when evaporating NiCr metal alloys during the fabrication process, deviation may still be encountered due to imperfect calibration, variation of thickness measurement, and other uncertainties. Therefore, it is worth investigating how the variation of resistance affects the performance of the divider (only 80 GHz divider was investigated). Assuming the length and width of the two NiCr resistors are fixed, only the resistor thickness changes. The change directly leads to change of sheet resistance and therefore change of resistor resistance. The thickness varied from 16.5 to 165 nm which corresponds to resistance of 200–20 Ω. As the simulation results shown in Fig. 5, an increase of the NiCr thickness (decrease of resistance) leads to the reduction of port isolation and better and wide matching at Port 2. The best performance is obtained when the NiCr thickness is 33 nm or 100 Ω for each resistor. Both port isolation and port matching become poorer as the thickness of the thin film NiCr increases further. These simulation results indicate that accurate control of resistor thickness ensures expected device performance.

III. DEVICE REALIZATION AND RESULTS

The dividers were fabricated on a 620 µm thick semi-insulating GaAs substrate with a dimension of 12 mm × 12 mm. All patterns were defined using electron beam lithography (EBL). A layer of 20 nm/100 nm thick Ti/Au was first deposited on the sample to form a set of alignment markers for subsequent registration layers. It was then followed by deposition of the 33 nm NiCr thin-film resistor layer. A 0.4 µm thick gold layer was then electron beam evaporated to form the CPW and S _CPS structures. Such a process of depositing the gold conductor layer after the NiCr layer allows solid contact at the NiCr/Au interface. The inverse process of depositing NiCr after Ti/Au may lead to discontinuities and open-circuits. The airbridges connecting the ground planes of the CPW and the symmetric CPS crossover for the phase inverter were formed by using EBL and a dry etch process [Reference Khalid, Li, Grant, Saha, Ferguson and Cumming17]. This airbridge development process provides a high degree of flexibility, simplicity, reliability, and compatibility with GaAs MMIC processes. Scanning electron microscope (SEM) images of the 80 GHz divider and its detailed airbridge crossover are shown in Fig. 7.

Fig. 7.

SEM images of (a) the whole fabricated 80 GHz power divider and (b) its air bridge crossover. The dark areas between ports in (a) are NiCr that is used to provide better field confinement within the component.

The dividers were tested using a pair of DC-110 GHz probes with pitch separation of 100 µm from GGB Industries and an Agilent PNA N5250C (10–110 GHz) on a Cascade semi-automated probe station [Reference Li, Lok, Khalid and Cumming18]. At millimeter-wave frequencies VNAs commonly have only two test ports making it difficult to test multi-port on-wafer devices. A common solution to this problem is that a series of duplicate devices are fabricated in a two-port configuration, and the other ports are terminated with 50 Ω thin-film resistors. Thus, multiple sets of measured data from different devices are obtained and reconstructed for the final S-parameters of the device [Reference Lopez-Diaz19]. This method assumes that all devices are identical but in fact this may not be true. Any variations from external causes such as fabrication may lead to change of the devices therefore reconstructed S-parameters are indeed not the real S-parameters of the device.

In this experiment we still used a two-port VNA however additional probes with matched standard loads were used to terminate the unused ports. This technique allowed the same device, rather than duplicate devices, to be tested as shown in Fig. 8(a). Calibration of the probes shown in Fig. 8(b) for the probe setup was performed using the Short-Open-Load-Reciprocal Thru (SOLR) method [Reference Basu and Hayden20]. A commercial alumina impedance standard substrate (P/N CS-15 from GGB Industries) containing right-angled standards was used. Since the ports of the power divider are orthogonal to each other, three separate calibrations, as shown in Fig. 8(c–e), were carried out on a standard probe station with two probes while a third probe was used as the broadband load. The S-parameters of the ring divider were reconstructed based on the three sets of two-port scattering parameter measurements.

Fig. 8.

On-wafer VNA measurement setup (10 MHz–110 GHz) for measuring devices with orthogonal ports and illustration of SOLR calibration procedure. (a) The actual three-port measurement setup with the unused port terminated by a third probe and a broadband matched load, (b) SOLR calibration setup for orthogonal ports, (c–e) illustration of three separate calibrations for three different probe positions.

Figure 9 shows the measured S-parameters and amplitude and phase imbalance responses of the 80 GHz power divider. The results are in good agreement with the simulations (Fig. 4). It can be seen (Fig. 9(a)) that isolation better than 20 dB is achieved across the bandwidth from 10 MHz to 110 GHz. The in-band insertion loss and port return losses are less than 1.3 dB and greater than 18 dB from 44 to 110 GHz. Figure 9(b) shows the measured amplitude and phase balances of the ring dividers. These indicate that the output amplitude and phase imbalance are within ±0.2 dB and ±10° in corresponding operation bandwidth.

Fig. 9.

(a) Measured S-parameters and (b) amplitudes and phase imbalance responses from the 80 GHz divider.

In order to verify the consistency of device performance, another power divider based on the same design criteria but operating at center frequency of 25 GHz was also designed, simulated, fabricated, and tested [Reference Li, Lok, Khalid and Cumming21]. The device parameters and values are listed in Table 1. The simulation and tested results are shown in Figs 10(a) and 10(b), respectively. One can see that there are two operation bands: one is at the center of 25 GHz and the other is at its third order of 25 GHz which is 75 GHz. Although the device can potentially work as a dual band power divider or at its second band only, its performance in terms of transmission, isolation, bandwidth, and port matching at the second band is not ideal. This may be further improved by optimizing the device design using narrower CPS and CPWs, but we here only concentrate on its fundamental operation band. It is obvious that the isolation is better than 18 dB across the entire tested bandwidth from 10 MHz to 110 GHz. The in-band insertion loss and port return losses are less than 0.6 dB and more than 15 dB from 15 to 32 GHz. Figure 9(c) shows that the measured amplitude and phase balances of the 25 GHz power dividers are ±0.5 dB and ±2° up to 50 GHz.

Fig. 10.

(a) Simulated S-parameters, (b) measured S-parameters, and (c) measured amplitudes and phase imbalance responses from a 25 GHz divider.