I. INTRODUCTION
In wireless communication, a receiver system processes a weak, desired signal along with large interferers. These interferers can saturate the receiver system, and the weak signal may experience a vanishingly small gain. Moreover, these interferers generate unwanted inter-modulation components in a signal channel because of non-linear characteristic of the circuit. The linearity specification and power capability should be large enough to avoid the distortion. To relax this hard condition, a surface acoustic wave (SAW) filter is commonly used to reject the interferer. However, the SAW filter is off-chip component which cannot be integrated, and the cost of fabrication increases sharply [Reference Razavi1, Reference Song, Kim, Han, Choi, Park and Kim2]. In these days, receiver systems without the SAW filter are actively researched.
A low-noise amplifier (LNA) amplifies not only the wanted signal but also the interferers because of the large bandwidth. Without the SAW filter, the large interferer amplified by LNA causes critical problems explained above. In a SAW-less receiver system, the LNA should play the role of the SAW filter to avoid these problems, requiring the blocker filtering LNA (BF-LNA) we are proposing. In other words, BF-LNA amplifies the wanted signal while attenuating the undesired large interferers. Figure 1 represents the interferer level at the input of the Bluetooth receivers and after the amplification by the normal LNA and BF-LNA. In case of Bluetooth, if the gain of frequency band under 2 GHz and over 3 GHz is below 0 dB, a mixer with P 1dB,in of −10 dBm can handle the signal and interferers and is not saturated. After the mixing stage, a finite impulse response (FIR) filter for the charge sampling mixer can sharply reject blockers [Reference Bagheri3].
(a) Interferer information of Bluetooth™ and the amplification by (b) normal LNA and (c) the blocker filtering LNA.
Conventional blocker filtering techniques employ down-conversion mixing to filter the out-of-band interferers at a low frequency, and their structures are relatively complex. Because of the additional mixer operation, they consume large power and occupy large chip size, and the noise is added in the complicated process. Moreover, the effects of various mismatches can cause degradation of the blocker rejection performance [Reference Safarian, Shameli, Rofougaran, Rofougaran and Flaviis4, Reference Darabi5].
In this letter, a new BF-LNA is presented. The proposed BF-LNA employs a differential amplifier structure with a common mode input, and filters the signal at one path using an on-chip notch filter. The two signals are subtracted by the current mirror active load. Finally, the only wanted signal is amplified, and the unwanted interferers are attenuated. Since the noise as well as signal are filtered out at one path, the noise figure is determined only by the amplification of the amplifying path, maintaining a low noise. To eliminate the SAW filter, the BF-LNA should have power capability large enough to handle the large interferers. It employs a common source amplifier structure with single transistor and draws a large DC current to ensure the output voltage swing. Figure 2 shows the operational principle of the proposed BF-LNA.
Principle of the proposed blocker filtering LNA.
II. BLOCKER FILTERING LOW-NOISE AMPLIFIER
Figure 3 shows schematic of the proposed BF-LNA. It adopts a differential amplifier structure but with a common-mode input. The input signals of each path of the differential amplifier are amplified and subtracted by the active load. The amplifications through the two paths should be the same to cancel the interferers properly, so the impedance balance of the active load is important. Because of the structure of the active load, the capacitances of the two loads are different. The balancing shunt capacitor C b is added at the right-side of the active load, given by
The largest interferer level of Bluetooth™ is −10 dBm at 400 MHz apart from the target frequency band [6] and the P 1dB,in of the LNA should be larger than −10 dBm. The amplifier employs a common source amplifier topology to achieve enough voltage headroom and uses large size transistors to draw enough current for the high-power capability. This large DC current leads to a little bit large power consumption, but the proposed BF-LNA does not need any additional block, i.e., down-conversion mixer, and the total current is not large.
Schematic of the proposed blocker filtering LNA.
A notch filter is placed at the one amplifying path. It is composed of series-connected on-chip inductor and capacitor. The inductor and capacitor are chosen to resonate at the signal frequency and the parasitic capacitance component of the interconnect should also be included:
The impedance at the resonance frequency of notch filter is zero, and the signal is shortened by the notch filter. At the left-hand side of differential amplifier with the filter, interferers are amplified while the wanted frequency band component is shorted. The active load has two roles. First, it is used as a load of the each amplifier. Second, it subtracts the right-side signal, which is amplified normally, from left-hand side signal, which is amplified and notched. The subtracted signal has only the wanted frequency component of the input signal and delivers to output node. The structure of the BF-LNA is very simple and the noise figure is low, determined by the single amplifying channel.
III. MEASUREMENT RESULTS
The BF-LNA is fabricated using a 0.13-μm CMOS process and the fabricated die photograph is represented in Fig. 4. It occupies an active area of 500 µm × 260 µm without pads. The measurement results of the proposed LNA are plotted in Figs 5 and 6. At 2.4 GHz, S 11 and S 22 are −8.5 dB and −28.7 dB, respectively. The gain is 11.4 dB and the noise figure is 1.85 dB. Attenuation performances at 400 MHz apart from the signal band are −13 dBc for the left sideband and −29 dBc for the right sideband. This attenuation level means that blockers of maximum −10 dBm under 2 GHz and over 3 GHz will not be amplified and only be attenuated. The attenuation level increases as further away from signal frequency band. The measured P 1 dB,in is −8.2 dBm, which is large enough to handle the signal and interferers of Bluetooth™ standard at the front-end without any filter and IIP3 is measured to be 1.46 dBm. The proposed BF-LNA amplifies only wanted signal and small blockers close to signal, and attenuates the large blockers of out-band, which causes saturation problem. The measurement results of these parameters are shown in Fig. 7. The dissipated power is 23.85 mW with DC voltage of 1.5 V. This large power dissipation is needed for the enough power handling capability but is not bad compared to the other filtering LNA. The performance of the circuit is summarized in Table 1.
The fabricated photograph of BF-LNA (chip size : 790 µm × 590 µm, active area without pads: 500 µm × 260 µm).
Simulation and measurement results of (a) S 11 and (b) S 22.
Simulation and measurement results of (a) power gain and (b) noise figure.
Measurement results of (a) P 1 dB and (b) IIP3.
Performance of the fabricated chip.
IV. CONCLUSIONS
In conclusion, the BF-LNA for a SAW-less receiver system is presented. By employing the differential amplifier structure, a notch filter and current mirror active load, the proposed BF-LNA amplifies the wanted signal while attenuates the unwanted large interferers. It employs common source amplifier structure and draws a large DC current to ensure the output voltage swing required for a large power handling capability. Even though it uses an on-chip inductor, the proposed BF-LNA can remove the SAW filter and reduce total size. The circuit structure is very simple but provides a good blocker filtering with a low-noise figure. The measured performances are good enough to be used in Bluetooth receiver system. The circuit is fabricated in 0.13-µm CMOS process, and it consumes 23.85 mW with 1.5 V supply voltage. The proposed BF-LNA exhibits a gain of 11.4 dB and a noise figure of 1.85 dB at 2.4 GHz. The attenuation levels of each sideband are −13 dBc and −29 dBc, respectively. The P 1 dB,in is −8.2 dBm and IIP3 is 1.46 dBm.
ACKNOWLEDGEMENTS
This work was supported by the Center for Advanced Transceiver Systems, which was sponsored by the next-generation new technology development programs of the Ministry of Knowledge and Economy (MKE), and supported by the WCU (World Class University) program through the Korea Science and Engineering Foundation funded by the Ministry of Education, Science and Technology (Project No. R31-2008-000-10100-0), and also supported by the ETRI SoC Industry Promotion Center, Human Resource Development Project for IT SoC Architect.
Heesong Seo received the B.S degree in electronic and electrical engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2007. He is currently working toward the Ph.D. degree at POSTECH. His research interests include CMOS RFIC for wireless communications, Digital RF sampling circuit for SDR system, and mixed mode signal processing IC design.
Hyejeong Song was born in Daegu, Korea, in 1982. She received the B.S. degree in electrical engineering from Kyungpook National University, Daegu, Korea, in 2006, and the M.S. degree in electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2008. She is currently working as researcher at POSTECH. Her interests include CMOS RF circuits for wireless communications, high-frequency analog circuit design, and mixed-mode signal-processing IC design.
Changjoon Park received the B.S. degree in materials science and electronic and electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2003, and is currently working toward the Ph.D. degree in electronic engineering with POSTECH. His interests include digital RF sampling circuit for software defined radio (SDR) systems, RF identification (RFID), CMOS RF circuits for wireless communications, high-frequency analog circuit design, and mixed-mode signal-processing IC design.
Jehyung Yoon was born in Seoul, Korea, in 1977. He received the B.S. degree in electrical and electronics engineering from Chung Ang University, Seoul, Korea, in 2004, the M.S. degree in electrical engineering from the Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2006, and is currently working toward the Ph.D. degree in electronic engineering at POSTECH. His research interests CMOS RF circuits and high frequency analog circuit design for wireless communications.
Inyoung Choi was born in Seoul, Korea, in 1984. He received the B.S degree in electronic and electrical engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2007. He is currently working toward the Ph.D. degree at POSTECH. His research interests include CMOS RFIC for wireless communications, Phase-locked loop, Baseband Circuits, and mixed mode signal processing IC design.
Bumman Kim received the Ph.D. degree in electrical engineering from Carnegie–Mellon University, Pittsburgh, PA, in 1979. From 1978 to 1981, he was engaged in fiber-optic network component research with GTE Laboratories Inc. In 1981, he joined the Central Research Laboratories, Texas Instruments Incorporated, where he was involved in development of GaAs power field effect transistors (FETs) and monolithic microwave integrated circuits (MMICs). He developed a large signal model of a power FET, dual-gate FETs for gain control, high-power distributed amplifiers, and various millimeter-wave MMICs. In 1989, he joined the Pohang University of Science and Technology (POSTECH), Pohang, Korea, where he is a Namko Professor with the Department of Electrical Engineering, and Director of the Microwave Application Research Center, where he is involved in device and circuit technology for RF integrated circuits (RFICs). He was a Visiting Professor of electrical engineering with the California Institute of Technology, Pasadena, in 2001. He has authored over 250 technical papers. Dr. Kim is a member of the Korean Academy of Science and Technology and the Academy of Engineering of Korea.
