Lattice mismatch and coefficient of thermal expansion mismatch

For a single-crystal film with lattice constant a _f on a single-crystal substrate with lattice constant a _s, a lattice mismatch, f _lattice, arises that is defined with positive stresses and strains being tensile, while negative values are compressive:

(1)$${f_{lattice}} = {{{a_s} - {a_f}} \over {{a_f}}}$$.

Furthermore, if the film is grown at temperature T _g and is then cooled down to room temperature, T _room, an additional coefficient of thermal expansion (CTE) mismatch stress develops:

(2)$${\sigma _{CTE}} = {Y_f}\left( {{T_g} - {T_{room}}} \right) \cdot \left( {{\alpha _f} - {\alpha _s}} \right)$$.

This mismatch depends on the difference between the film’s (α _f) and substrate’s (α _s) CTEs and on the film’s elastic modulus, Y _f. Materials that are highly dissimilar in terms of lattice constants and CTEs, or grown at high temperatures, will face more severe challenges.

With metal–organic chemical vapor deposition (MOCVD) growth temperatures ≥700°C for III–As/P and ≥1000°C for III–N materials, significant stresses build up between the epitaxially grown films and the substrates when the wafers and device layers are ultimately cooled down to room temperature. Bowing of the wafer in proportion to its size occurs and, if large enough, will impact fabrication yields. Device performance might also be affected, as strain effects modify both the electrical and optical properties of the materials. In extreme cases, the large internal film stresses lead to wafer fragility issues that further impact device and circuit yield.^{Reference Zhu, McAleese, McLaughlin, Häberlen, Salcianu, Thrush, Kappers, Phillips, Lane, Wallis, Martin, Astles, Thomas, Pakes, Heuken and Humphreys5}

Metamorphic graded buffers for lattice engineering

As described in the introductory article in this issue, graded buffer layers are commonly used for metamorphic transistor devices. Because dislocations have a negative impact on devices, the goal is to keep the threading dislocation density (TDD) low enough so as not to affect subsequent device operation while engineering the lattice constant. This is generally achieved by growing one or more buffer layers with intermediate lattice constants to bridge the difference between the starting lattice constant and the desired ending lattice constant. III–V compound semiconductors especially benefit from metamorphic epitaxy, as they can readily form alloys with different lattice constants. In particular, the III–As/P and III–N material systems have been used extensively for transistors due to their favorable electronic properties. Cross-sectional transmission electron microscope (TEM) images of typical graded buffers used in the III–As/P and III–N material systems are shown in Figure 1.

Figure 1.

Cross-sectional transmission electron microscope images of an (a) InAlAs continuously graded buffer (taken in two-beam diffraction condition with diffraction vector, g = 〈022〉); and an (b) AlGaN step-graded buffer (taken with g = 〈0002〉).^{Reference Lee, Bao, Kohen, Huang, Lee, Fitzgerald and Tan47}

III–As/P metamorphic epitaxy

In the III–As/P material system, compositionally graded In_xAl_1–xAs buffers are generally used for metamorphic transistor growth due to their larger bandgap which results in low buffer leakage currents.^{Reference Hoke and Whelan6} This is especially critical for high-speed radio frequency (RF) devices, the general application focus for As/P transistors, and is why InAlAs is strongly preferred, despite the greater difficulties of working with Al-containing materials. Starting from a GaAs (or AlAs) layer, the InAlAs buffer is typically step-graded or continuously graded, by changing the In mole fraction of the alloy in discrete steps or in a continuous fashion, respectively. InGaP-graded buffers have also been used due to their significantly better thermal conductivity, which is important for high-power devices.^{Reference Ng, Radhakrishnan and Wang4}

Slower composition grading rates moderate the pace of strain incorporation into the growing films (generally resulting in lower TDD), but result in thicker metamorphic buffers that might exacerbate CTE mismatch issues. Strain fields that develop as lattice-mismatch strain is added and subsequently relaxed lead to characteristic “crosshatch” surface roughness.^{Reference Lee and Fitzgerald7} This surface roughness must be managed such that dislocation motion is not impeded during metamorphic buffer growth, and channel mobility is not significantly affected. Higher growth temperatures are generally preferred to enhance glide velocities and mismatch relaxation in III–As/P materials. However, too high a growth temperature can lead to excess dislocation nucleation and may also cause increased surface and interface roughness.

As mentioned in the article by France et al. in this issue, phase separation is a key challenge in metamorphic growth of III–V materials. This affects graded buffer quality in two ways: (1) Strain fields at the boundaries of different compositional domains can arrest dislocation glide; (2) lattice mismatch at the boundaries can itself promote the nucleation of excess dislocations.^{Reference Quitoriano and Fitzgerald8} With particular relevance to metamorphic transistors, phase separation has been observed in InGaAs, InAlAs, InGaP, and AlGaN alloys,^{Reference Quitoriano and Fitzgerald8–Reference Chen, Chua and Miao10} the most common ternary alloys used in metamorphic transistors and their associated buffer layers. Phase separation is governed by surface thermodynamics, but it can also be kinetically suppressed^{Reference Yang, Bulsara, Lee and Fitzgerald11} by growing films at low temperatures. Thus, there are generally two growth temperature regimes used to obtain high-quality metamorphic buffers—a high-temperature window where miscibility gaps and phase separation are reduced while dislocation glide is enhanced, and a low-temperature window where phase separation is ameliorated by kinetically reducing atomic mobility. It should be noted at this point that phase separation is also mediated by the presence of strain.^{Reference Lee and Fitzgerald12}

III–N metamorphic epitaxy

With no readily available large-area GaN or AlN bulk substrates on which III–N devices can be directly grown, metamorphic epitaxy is a necessity. The most commonly used substrates for III–N epitaxy are Si (111), SiC, and sapphire. Their key parameters are shown in Table I,¹³ along with values for GaN and AlN.

Table I.

Key parameters of important materials in III–N epitaxy.¹³

*to (11$\bar 2$0) planes.

Note: a, lattice parameter; a _sub, substrate lattice parameter; a _GaN, GaN lattice parameter; 4H/6H, SiC polytypes.

Si (111) wafers are desirable due to the availability of relatively low-cost 200-mm or larger diameter wafers. However, they present the most challenging lattice-mismatch situation at +20.8%. Additionally, the CTE of Si is less than one-half that of GaN, and thus, the GaN films contract far faster than the Si substrate during cooldown from the high nitride growth temperatures. Even if the wafer does not crack under the high tensile stress, it would likely possess a significant bow, especially at larger wafer sizes, making subsequent device processing challenging. Furthermore, there are a host of other issues related to nucleating and growing III–N materials on Si,^{Reference Semond14} including meltback etching, where uncontrolled Ga and Si alloying at the GaN–Si interface^{Reference Dadgar15} rapidly destroys the growing nitride film once the process initiates. Alternatively, AlN nucleation layers and subsequent growth of partially relaxed (Al)GaN layers with compressive strain can compensate for the tensile stress that builds up during cooldown due to CTE mismatch. This provides a measure of wafer bow control and can reduce the propensity of the GaN-on-Si wafer to crack during growth and cooldown through balancing the internal stresses of the different layers.

Nanopatterned metamorphic epitaxy

With increasing implementation of high strain layers and three-dimensional (3D) device structures such as fin field-effect transistors (finFETs), advanced CMOS foundries are also exploring novel methods to implement metamorphic epitaxy such that III–V channels can be directly incorporated into the CMOS processing line. As mismatched epitaxial growth in small growth windows has been shown to result in reduced dislocation densities,^{Reference Fitzgerald16} many different nanopatterned growth strategies have been introduced over the years, and two are briefly reviewed here.

In one approach, narrow on-axis (001) silicon ridges are defined by closely spaced shallow trench isolation (STI) features. Chemical etching of the ridges results in trenches between the STI features with V-groove Si (111) surfaces at the bottom of the trench on which MOCVD is used to selectively grow a relaxed InP metamorphic buffer. The narrow STI sidewalls provide defect trapping that eliminate threading dislocations, twins, and stacking faults. This buffer is partially removed, and an InGaAs channel that is lattice-matched to the InP buffer is grown. Implementing a gate-all-around FET device structure has yielded devices with a channel length (L _G) of 60 nm with peak transconductance of 1030 µS/µm and a subthreshold swing of 125 mV/dec, which are values that compare favorably with other reported results.^{Reference Waldron, Merckling, Teugels, Ong, Sebaai, Barla, Collaert and Thean17}

In another approach, a silicon-on-insulator wafer is first patterned and etched to produce a silicon seed region. MOCVD is then used to laterally grow InAs nanowires in a process termed template-assisted selective epitaxy. With horizontal III–V channels that demonstrate a Hall mobility of 5400 cm²/Vs, multiple-gate FETs exhibit a peak transconductance of 1000 µS/µm at a drain–source voltage (V _DS) of 0.5 V.^{Reference Schmid, Borg, Moselund, Gignac, Breslin, Bruley, Cutaia and Riel18}

Metamorphic InGaAs HEMTs/MOSFETs

In the III–As/P material system, HEMT characteristics are determined mostly by the (In)GaAs channel material. Metamorphic buffers are used to tune the lattice constant to allow access to a specific channel (InGaAs) and barrier (typically InAl(Ga)As) material combination. Higher indium mole fractions in the channel result in higher mobility and faster devices. Additionally, delta doping is usually employed to provide the carriers in the channel and to reduce the amount of parasitic conduction in the low-mobility barrier layer.^{Reference Kim, Tian and Littlejohn26}

HEMTs with high (≥53%) indium mole fraction InGaAs channels are used for ultrahigh-speed applications, as they have achieved f _T (unity gain cutoff frequency) and f _max (maximum oscillation frequency) values of several hundreds of GHz, which makes them suitable for THz or near-THz applications.^{Reference Kim, Brar and del Alamo27,Reference Chang, Kuo, Hsu, Chiang and Miyamoto28} Metamorphic epitaxy has been successfully used by many groups to obtain mHEMTs on GaAs substrates with ≥53% indium mole fraction InGaAs channels, analogous to lattice-matched or pseudomorphic HEMTs on InP substrates. Similar performances for f _T, transconductance (g _m), gain, noise figure (a measure of the excess noise in the device output over and above that attributable to thermal noise), and reliability have been reported for mHEMT and pseudomorphic HEMT (pHEMT) devices;^{Reference Ng, Radhakrishnan and Wang4,Reference Komiak, Smith, Duh, Xu and Chao29–Reference Wu, Liu, Li, Li, Hu, Xi and Zhao31} this suggests that the metamorphic buffers did not detract from device performance. For instance, deeply scaled GaAs mHEMTs, such as those reported by Leuther et al.^{Reference Leuther, Koch, Tessmann, Kallfass, Merkle, Massler, Loesch, Schlechtweg, Saito and Ambacher32} and Kim et al.,^{Reference Kim, Brar and del Alamo27} have attained f _T values of over 660 GHz and maximum linear transconductance, g _m,max >2500 mS/mm for devices with channel lengths ranging from 20–40 nm. These values are comparable to those reported for InP pHEMT devices with similar channels and gate dimensions.^{Reference Chang, Kuo, Hsu, Chiang and Miyamoto28,Reference Kim and del Alamo33} Komiak et al. reported that their mHEMTs had lower additive phase noise at low operating currents than lattice-matched HEMTs on InP substrates, making them superior devices for low-noise amplifier circuits.^{Reference Komiak, Smith, Duh, Xu and Chao29} They surmised that this unexpected result could be due to the differences in surface trapping effects between the two types of devices.

InGaAs mHEMTs with InGaAs channels with approximately 30–40% indium mole fraction have shown a good balance of speed and power handling/breakdown.^{Reference Zaknoune, Ardouin, Cordier, Bollaert, Bonte and Theron3,Reference Kim, Koh, Choi, Kim, Kwon and Seo34} Kim et al. reported 50-nm In_0.35Ga_0.65As channel devices that were grown on metamorphic InAlAs buffers graded from AlAs to In_0.45Al_0.55As and capped with a grade-back layer of In_0.4Al_0.6As. The devices achieved f _T and f _max values of 216 and 400 GHz, respectively, with a relatively high OFF-state breakdown voltage of –7.2 V, making them excellent candidates for high-gain low-noise amplifiers.^{Reference Kim, Koh, Choi, Kim, Kwon and Seo34}

Metamorphic insulated gate devices such as MOSHEMTs and MOSFETs have also been explored. Zhou et al.^{Reference Zhou, Tang, Li, Chen and Lau35} compared In_0.6Ga_0.4As channel HEMT and MOSHEMT devices on GaAs wafers fabricated using the same starting wafer material. Affirming the benefits of a MOS gate structure, the gate leakage current of the MOSHEMT was five orders of magnitude lower than that of a similar HEMT device. The same group has also reported comparable results for similar metamorphic MOSHEMTs formed on Si wafers.^{Reference Li, Zhou, Tang and Lau36} Metamorphic MOSHEMTs have also been shown to be less susceptible to impact ionization as compared with HEMTs, resulting in a reduction of the kink effect in device I _d–V _d (drain–current–drain voltage) curves.^{Reference Lee, Yeh, Hsu, Liu and Chou37} While surface-channel MOSFETs have poorer high-frequency performance due to lower channel carrier mobility, their superior gate control makes them promising devices for scaling in the context of Moore’s Law and CMOSs. They also possess better ON-state resistance due to the absence of a resistive barrier layer, making them highly suited for logic devices.^{Reference del Alamo, Antoniadis, Guo, Kim, Kim, Lin, Lu, Vardi and Zhao19} Both wafer-scale^{Reference Huang, Chang, Chen, Fan, Lin, Lin, Chu, Lee, Khaderbad, Chen, Lin, Chen, Lin, Lin, Chang, Yang, Leung, Yeo, Jang, Hwang and Diaz38} and selective-area^{Reference Waldron, Merckling, Teugels, Ong, Sebaai, Barla, Collaert and Thean17} metamorphic growth approaches are being explored.

Metamorphic heterostructures have also been grown on lattice-engineered substrates.^{Reference Yadav, Saeid, Gong, Kohen, Nguyen, Lee, Lee, Yeo, Antoniadis and Fitzgerald39}Figure 3 shows a cross-sectional TEM image of a metamorphic In_0.3Ga_0.7As/InAlAs HEMT heterostructure on Si. Hall measurements revealed a carrier mobility of 5400–5700 cm²/Vs and sheet-carrier densities of approximately 2 × 10¹² cm^–2. Typical I _d–V _d results from L _g ∼200-nm MOSHEMT devices fabricated on 200-mm-diameter wafer material are shown in Figure 4. The InGaAs cap was co-doped with Te and Si to a level of >1 × 10¹⁹ cm^–3, and the threshold voltage, V _th, was approximately 0.2 V. The device exhibited good pinch-off characteristics, with low drain current (i.e., I _d < 10^–3 µA/µm) below threshold, and clearly operates as an enhancement mode device. Good ON-state drain currents are achieved, but transconductance collapse is observed at higher gate voltages.

Figure 3.

Cross-sectional transmission electron microscope image of an In_0.3Ga_0.7As/InAlAs high-electron-mobility transistor (HEMT) heterostructure grown on a 200-mm Si wafer. The inset is a high magnification image of the HEMT device layers. The device layers are relatively flat, and no threading dislocations can be seen in the cross section, suggesting a threading dislocation density of <1 × 10⁸ cm^–2.

Figure 4.

Drain current–drain voltage (I _d–V _d) curves for a channel length L _g = 200-nm metal oxide semiconductor high-electron-mobility transistor device fabricated from heterostructures grown on 200-mm Si wafers. The various curves represent different gate-to-source (V _GS) voltages, starting from V _GS = 0.1 V for the lowest curve and increasing in steps of 0.3 V to V _GS = 1.9 V for the top curve. ON-state current compares favorably with similar devices reported in the literature, though transconductance appears to decrease with increasing gate overdrive (i.e., V _GS–V _th). Further device design optimization will be needed to address this. Note: V _GS, gate-to-source voltage; V _th, threshold voltage.

Metamorphic GaN HEMTs/MOSFETs

III–N HEMTs have, to date, been almost exclusively metamorphic devices due to the lack of native bulk substrates. They are exemplified by Al(Ga)N/GaN devices, as depicted in Figure 2b. The dissimilarity of the two polarization components at the AlGaN barrier/GaN buffer-layer heterojunction interface leads to the formation of a deep triangular potential well containing a high-density 2DEG that serves as the conducting channel for the HEMT. Higher aluminum mole fraction barriers result in greater polarization dissimilarity between the barrier and the channel, leading to higher 2DEG sheet-carrier density. This has led to the use of channels with AlN/GaN heterojunctions, in the form of a 1–2-nm-thick AlN interlayer between the GaN channel and the capping AlGaN barrier layer.

The best devices have typically been achieved on SiC substrates due to the lower lattice mismatch and CTE mismatch they present for III–N growth. AlGaN/GaN HEMT heterostructures on SiC substrates have been reported to possess Hall mobilities approaching 2000 cm²/Vs and 2DEG carrier densities approaching 10¹³ cm^–2. This allows L _g = 0.25-µm devices to provide output power levels of 7 W/mm at 40 V for 18 GHz devices.^{Reference Pengelly, Wood, Milligan, Sheppard and Pribble40} Even with their relatively modest Hall mobilities, AlGaN/GaN HEMTs have demonstrated very high f _T and f _max values on the order of several hundred GHz^{Reference Chung, Hoke, Chumbes and Palacios41} due to their high transconductance. Even higher frequency performance has been obtained in InAlN barrier devices because of their higher 2DEG density.^{Reference Yue, Hu, Guo, Sensale-Rodriguez, Li, Wang, Faria, Fang, Song, Gao, Guo, Kosel, Snider, Fay, Jena and Xing42}

III–N MOSFETs have also been demonstrated in which the conducting channel is formed in a GaN layer without an adjacent Al(Ga)N barrier. There is therefore no 2DEG and no commensurately high carrier mobility.^{Reference Lee, Cho, An, Bae, Lee, Lee and Hahm43,Reference Im, Ha, Kim, Lee, Kim, Hahm and Lee44} These devices are, however, true enhancement-mode devices with excellent ON-state current to OFF-state current (I _ON/I _OFF) ratios and low-gate leakage, making them well suited for logic and power applications.