Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- 3 Boolean algebra
- 4 CMOS logic circuits
- 5 Delay and power of CMOS circuits
- 6 Combinational logic design
- 7 VHDL descriptions of combinational logic
- 8 Combinational building blocks
- 9 Combinational examples
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
9 - Combinational examples
from Part II - Combinational logic
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- 3 Boolean algebra
- 4 CMOS logic circuits
- 5 Delay and power of CMOS circuits
- 6 Combinational logic design
- 7 VHDL descriptions of combinational logic
- 8 Combinational building blocks
- 9 Combinational examples
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
In this chapter we work through several examples of combinational circuits to reinforce the concepts in the preceding chapters. A multiple-of-3 circuit is another example of an iterative circuit. The tomorrow circuit from Section 1.4 is an example of a counter circuit with subcircuits for modularity. A priority arbiter is an example of a building-block circuit – built using design entities described in preceding chapters. Finally, a circuit designed to play tic-tac-toe gives a complex example combining many concepts.
MULTIPLE-OF-3 CIRCUIT
In this section we develop a circuit that determines whether an input number is a multiple of 3. We implement this function using an iterative circuit (like the magnitude comparator of Section 8.6). A block diagram of an iterative multiple-of-3 circuit is shown in Figure 9.1. Each stage performs, in binary, a step of long division of the input number by 3, passing along the remainder but discarding the quotient. The circuit checks the input number one bit at a time starting at the MSB. At each bit, we compute the remainder so far (0, 1, or 2). At the LSB we check whether the overall remainder is 0. Each bit cell takes the remainder so far to its left, and one bit of the input, and computes the remainder so far to its right.
The VHDL design entity for the bit cell of our iterative multiple-of-3 circuit is shown in Figure 9.2. The remainder in remin represents the remainder from the neighboring bit to the left, and hence has a weight of 2 relative to the current bit position. In our neighboring bit this signal represented a remainder of 0, 1, or 2. However, in the present bit, this value is shifted to the left by one bit and it represents a value of 0, 2, or 4. Hence we can concatenate remin with the current bit of the input, input, to form a three-bit binary number and then take the remainder (mod 3) of this number. A case statement is used to compute the new remainder.
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- Digital Design Using VHDLA Systems Approach, pp. 199 - 218Publisher: Cambridge University PressPrint publication year: 2015
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