Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- 26 Asynchronous sequential circuits
- 27 Flip-flops
- 28 Metastability and synchronization failure
- 29 Synchronizer design
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
27 - Flip-flops
from Part VII - Asynchronous logic
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- 26 Asynchronous sequential circuits
- 27 Flip-flops
- 28 Metastability and synchronization failure
- 29 Synchronizer design
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
Flip-flops are among the most critical circuits in a modern digital system. As we have seen in previous chapters, flip-flops are central to all synchronous sequential logic. Registers (built from flip-flops) hold the state (both control and data state) of all of our finite-state machines. In addition to this central role in logic design, flip-flops also consume a large fraction of the die area, power, and cycle time of a typical digital system.
Until now, we have considered a flip-flop as a black box. In this chapter, we study the internal workings of the flip-flop. We derive the logic design of a typical D flip-flop and show how the timing properties introduced in Chapter 15 follow from this design.
We first develop the flip-flop design informally – following an intuitive argument. We start by developing the latch. The implementation of a latch follows directly from its specification. From the implementation we can then derive the setup, hold, and delay times of the latch. We then see how to build a flip-flop by combining two latches in a master–slave arrangement. The timing properties of the flip-flop can then be derived from its implementation.
Following this informal development, we then derive the design of a latch and flip-flop using flow-table synthesis. This serves both to reinforce the properties of these storage elements and to give a good example of flow-table synthesis. We introduce the concept of state equivalence during this derivation. This formal derivation can be skipped by a casual reader.
INSIDE A LATCH
A schematic symbol for a latch is shown in Figure 27.1(a), and waveforms illustrating its behavior and timing are shown in Figure 27.1(b). A latch has two inputs, data d and enable g, and one output, q. When the enable input is high, the output follows the input. When the enable input is low, the output holds its current state.
As shown in Figure 27.1(b), a latch, like a flip-flop, has a setup time ts and a hold time th. An input must be setup ts before the enable falls and held for th after the enable has fallen in order for the input value to be correctly stored. Latch delay is characterized by both delay from the enable rising to the output changing, tdGQ, and delay from the data input changing to the output changing, tdDQ.
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- Digital Design Using VHDLA Systems Approach, pp. 566 - 579Publisher: Cambridge University PressPrint publication year: 2015
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