Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- 21 System-level design
- 22 Interface and system-level timing
- 23 Pipelines
- 24 Interconnect
- 25 Memory systems
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
24 - Interconnect
from Part VI - System design
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- 21 System-level design
- 22 Interface and system-level timing
- 23 Pipelines
- 24 Interconnect
- 25 Memory systems
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
The interconnect between modules is as important a component of most systems as the modules being connected. As described in Section 5.6, wires account for a large fraction of the delay and power in a typical system. A wire of just 3 μm in length has the same capacitance (and hence dissipates the same power) as a minimum-sized inverter. A wire of about 100 μm in length dissipates about the same power as one bit of a fast adder.
Whereas simple systems are connected with direct point-to-point connections between modules, larger and more complex systems are better organized with a bus or a network. Consider an analogy to a telephone or intercom system. If you need to talk to only two or three people, you might use a direct line to each person you need to talk to. However, if you need to talk to hundreds of people, you would use a switching system, allowing you to dial any of your correspondents over a shared interconnect.
ABSTRACT INTERCONNECT
Figure 24.1 shows a high-level view of a system using a general interconnect (e.g., a bus or a network). A number of clients are connected to the network by a pair of links to and from the interconnect. The links may be serialized (Section 22.3), and flow control is required on at least the link into the interconnect – to back-pressure the client in the event of contention.
To communicate, client S (the source client), transmits a packet over the link iS into the interconnect. The packet includes, at minimum, a destination address, D, and a payload, P, which may be of arbitrary (or even variable) length. The interconnect, possibly with some delay due to contention, delivers P to client D over link oD out of the interconnect. The payload P may contain a request type (e.g., read or write), a local address within D, and data or other arguments for a remote operation. Because the interconnect is addressed, any client A can communicate with any client B while requiring only a single pair of unidirectional links on each client module.
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- Digital Design Using VHDLA Systems Approach, pp. 521 - 531Publisher: Cambridge University PressPrint publication year: 2015
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