Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- 21 System-level design
- 22 Interface and system-level timing
- 23 Pipelines
- 24 Interconnect
- 25 Memory systems
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
22 - Interface and system-level timing
from Part VI - System design
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- 21 System-level design
- 22 Interface and system-level timing
- 23 Pipelines
- 24 Interconnect
- 25 Memory systems
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
System-level timing is generally driven by the flow of information through the system. Because this information flows through the interfaces between modules, system timing is tightly tied to interface specification. Timing is determined by how modules sequence information over these interfaces. In this chapter we will discuss interface timing and illustrate how the operation of the overall system is sequenced via these interfaces, drawing on the examples introduced in Chapter 21.
INTERFACE TIMING
Interface timing is a convention for sequencing the transfer of data. To transfer a datum from a source module S to a destination module D, we need to know when the datum is valid (i.e., when the source module S has produced the datum and placed it on its interface pins) and when D is ready to receive the datum (i.e., when D samples the datum from its interface pins). We have already seen examples of interface timing in the interfaces between the modules of factored state machines in Chapter 17. In the remainder of this section, we look at interface timing in more depth.
Always valid timing
As the name implies, an always valid signal (Figure 22.1), is always valid. An interface with only always valid signals does not require any sequencing signals.
It is important to distinguish an always valid signal from a periodically valid signal (Section 22.1.2) with a period of one clock cycle. An always valid signal represents a value that can be dropped or duplicated. A temperature sensor that constantly outputs an eight-bit digital value representing the current temperature is an example of such a signal. We could pass this signal to a module operating at twice the clock rate (duplicating temperature signals) or a module operating at half the clock rate (dropping temperature values), and the output of the module still represents the current temperature (with perhaps a slight lag).
The state interfaces in the Pong game of Figure 21.2 are another example of always valid interfaces. The mode, ballPos, leftPadY, rightPadY, and score signals are all examples of always valid signals. Each of these signals always represents the current value of a state variable.
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- Digital Design Using VHDLA Systems Approach, pp. 479 - 496Publisher: Cambridge University PressPrint publication year: 2015
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