Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- 26 Asynchronous sequential circuits
- 27 Flip-flops
- 28 Metastability and synchronization failure
- 29 Synchronizer design
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
28 - Metastability and synchronization failure
from Part VII - Asynchronous logic
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- 26 Asynchronous sequential circuits
- 27 Flip-flops
- 28 Metastability and synchronization failure
- 29 Synchronizer design
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
What happens when we violate the setup- and hold-time constraints of a flip-flop? Until now, we have considered only the normal behavior of a flip-flop when these constraints are satisfied. In this chapter we investigate the abnormal behavior that occurs when we violate these constraints. We will see that violating setup and hold times may result in the flip-flop entering a metastable state in which its state variable is neither a 1 nor a 0. It may stay in this metastable state for an indefinite amount of time before arriving at one of the two stable states (0 or 1). This synchronization failure can lead to serious problems in digital systems.
To stretch an analogy, flip-flops are a lot like people. If you treat them well, they will behave well. If you mistreat them, they behave poorly. In the case of flip-flops, you treat them well by observing their setup and hold constraints. As long as they are well treated, flip-flops will function properly, never missing a bit. If, however, you mistreat your flip-flop by violating the setup and hold constraints, it may react by misbehaving – staying indefinitely in a metastable state. This chapter explores what happens when these good flip-flops go bad.
SYNCHRONIZATION FAILURE
When we violate the setup- or hold-time constraints of a D flip-flop, we can put the internal state of the flip-flop into an illegal state. That is, the internal nodes of the flip-flop can be left at a voltage that is neither a 0 nor a 1. If the output of the flip-flop is sampled while it is in this state, the result is indeterminate and possibly inconsistent. Some gates may see the flip-flop output as a 0, while others may see it as a 1, and still others may propagate the indeterminate state.
Consider the following experiment with a D flip-flop. Initially both d and clk are low. During our experiment, they both rise. If signal d rises ts before clk, the output q will be 1 at the end of the experiment. If signal clk rises th before d, the output q will be 0 at the end of the experiment.
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- Digital Design Using VHDLA Systems Approach, pp. 580 - 591Publisher: Cambridge University PressPrint publication year: 2015
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