Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- 14 Sequential logic
- 15 Timing constraints
- 16 Datapath sequential logic
- 17 Factoring finite-state machines
- 18 Microcode
- 19 Sequential examples
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
18 - Microcode
from Part IV - Synchronous sequential logic
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- 14 Sequential logic
- 15 Timing constraints
- 16 Datapath sequential logic
- 17 Factoring finite-state machines
- 18 Microcode
- 19 Sequential examples
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
Implementing the next-state and output logic of a finite-state machine using a memory array gives a flexible way of realizing an FSM. The function of the FSM can be altered by changing the contents of the memory. We refer to the contents of the memory array as microcode, and a machine realized in this manner is called a microcoded FSM. Each word of the memory array determines the behavior of the machine for a particular state and input combination, and is referred to as a microinstruction.
We can reduce the required size of a microcode memory by augmenting the memory with special logic to compute the next state, and by selectively updating infrequently changing outputs. A single microinstruction can be provided for each state, rather than one for each state × input combination, by adding an instruction sequencer and a branch microinstruction to cause changes in control flow. Bits of the microinstruction can be shared by different functions by defining different microinstruction types for control, output, and other functions.
SIMPLE MICROCODED FSM
Figure 18.1 shows a block diagram of a simple microcoded FSM. A memory array holds the next-state and output functions. Each word of the array holds the next state and output for a particular combination of input and current state. The array is addressed by the concatenation of the current state and the inputs. A pair of registers holds the current state and current output.
In practice, the memory could be realized as a RAM or EEPROM allowing software to reprogram the microcode. Alternatively, the memory could be a ROM. With a ROM, a new mask set is required to reprogram the microcode. However, this is still advantageous because changing the program of the ROM does not otherwise alter the layout of the chip. Some ROM designs even allow the program to be changed by altering only a single metal-level mask – reducing the cost of the change. Some designs take a hybrid approach, putting most of the microcode into ROM (to reduce cost) but keeping a small portion of microcode in RAM. A method is provided to redirect an arbitrary state sequence into the RAM portion of the microcode to allow any state to be patched using the RAM.
Information
- Type
- Chapter
- Information
- Digital Design Using VHDLA Systems Approach, pp. 398 - 430Publisher: Cambridge University PressPrint publication year: 2015
Accessibility standard: Unknown
Why this information is here
This section outlines the accessibility features of this content - including support for screen readers, full keyboard navigation and high-contrast display options. This may not be relevant for you.Accessibility Information
Accessibility compliance for the PDF of this chapter is currently unknown
and may be updated in the future.