Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- 14 Sequential logic
- 15 Timing constraints
- 16 Datapath sequential logic
- 17 Factoring finite-state machines
- 18 Microcode
- 19 Sequential examples
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
19 - Sequential examples
from Part IV - Synchronous sequential logic
Published online by Cambridge University Press: 01 February 2019
Book contents
- Frontmatter
- Contents
- Preface
- Acknowledgments
- Part I Introduction
- Part II Combinational logic
- Part III Arithmetic circuits
- Part IV Synchronous sequential logic
- 14 Sequential logic
- 15 Timing constraints
- 16 Datapath sequential logic
- 17 Factoring finite-state machines
- 18 Microcode
- 19 Sequential examples
- Part V Practical design
- Part VI System design
- Part VII Asynchronous logic
- Part VIII Appendix: VHDL coding style and syntax guide
- References
- Index of VHDL design entities
- Subject index
Summary
This chapter gives some additional examples of sequential circuits. We start with a simple FSM that reduces the number of 1s on its input by a factor of 3 to review how to draw a state diagram from a specification and how to implement a simple FSM in VHDL. We then implement an SOS detector to review factoring of state machines. Next, we revisit our tic-tactoe game from Section 9.4 and build a datapath sequential circuit that plays a game against itself using the combinational move generator we previously developed. We illustrate the use of table-driven sequential circuits and composing circuits from sequential building blocks like counters and shift registers by building a Huffman encoder and decoder. The encoder uses table lookup along with a counter and shift register, while the decoder traverses a tree data structure stored in a table.
DIVIDE-BY-3 COUNTER
In this section we will design a finite-state machine that outputs a high signal on the output for one cycle for each three cycles the input has been high. More specifically, our FSM has a single input called input and a single output called output. When input is detected high for the third cycle (and sixth, ninth, etc.), output will go high for exactly one cycle. This FSM divides the number of pulses on the input by 3. It does not divide the binary number represented by the input by 3.
A state diagram for this machine is shown in Figure 19.1. At first it may seem that we can implement this machine with three states; however, four are required. We need states A to D to distinguish having seen the input high for zero, one, two, or three cycles so far. The machine resets to state A. It sits in this state until the input is high on a rising clock edge, at which time it advances to state B. The second high input takes the machine to C, and the third high input takes the machine to D, where the output goes high for one cycle. We can't simply have this third high input take us back to A because we need to distinguish having seen three cycles of high input – in which case the output goes high – from having seen zero cycles of high input.
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- Digital Design Using VHDLA Systems Approach, pp. 431 - 450Publisher: Cambridge University PressPrint publication year: 2015
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