Book contents
- Frontmatter
- Dedication
- Contents
- Preface
- Acknowledgments
- Disclaimer
- 1 Introduction
- 2 Electrostatic Discharge Characterization Methods
- 3 Process Technology Impact
- 4 Design of Electrostatic Discharge Protection Devices
- 5 High-Current Electrostatic Discharge Behavior
- 6 Advanced Input/Output Electrostatic Design
- 7 Ultra-Large-Scale Integration CMOS Technologies
- 8 Electrostatic Discharge Basics of Aluminum Gallium Nitride/Gallium Nitride High-Electron Mobility Transistors
- 9 Basics of 1D/2D Materials, Thin Film Transistors and Their Electrostatic Discharge Failures
- 10 Challenges in Novel Packaging Technologies
- Glossary
- Index
- References
7 - Ultra-Large-Scale Integration CMOS Technologies
Published online by Cambridge University Press: 18 July 2026
Book contents
- Frontmatter
- Dedication
- Contents
- Preface
- Acknowledgments
- Disclaimer
- 1 Introduction
- 2 Electrostatic Discharge Characterization Methods
- 3 Process Technology Impact
- 4 Design of Electrostatic Discharge Protection Devices
- 5 High-Current Electrostatic Discharge Behavior
- 6 Advanced Input/Output Electrostatic Design
- 7 Ultra-Large-Scale Integration CMOS Technologies
- 8 Electrostatic Discharge Basics of Aluminum Gallium Nitride/Gallium Nitride High-Electron Mobility Transistors
- 9 Basics of 1D/2D Materials, Thin Film Transistors and Their Electrostatic Discharge Failures
- 10 Challenges in Novel Packaging Technologies
- Glossary
- Index
- References
Summary
This chapter explores the electrostatic discharge (ESD) behavior of ultra-large-scale integration (ULSI) complementary metal oxide semiconductor (CMOS) technologies, focusing on fin-type field effect transistor (FinFET),nanosheet FETs (NSHFETs), and nanowire FETs (NWFETs). It begins with an in-depth analysis of ESD robustness in FinFETs fabricated on both SOI and bulk substrates, examining the impact of layout and process parameters such as gate length, fin width, doping, silicide blocking, and strain engineering. The chapter then investigates failure mechanisms under ESD stress, highlighting localized heating and material degradation. The transition to NSHFETs is detailed, emphasizing their gate-all-around (GAA) architecture, enhanced electrostatics, and sensitivity to sheet width, thickness, and stacking. Process challenges such as selective etching, sidewall metal contacts, and threshold voltage tuning are addressed. Finally, the chapter covers NWFET design parameters, including variability control, channel dimensions, and parasitic effects. Overall, it provides critical insights into the evolving landscape of ESD design for next-generation complementary metal oxide semiconductor (CMOS) nodes.
Keywords
Electrostatic Discharge (ESD)Fin-type Field Effect Transistor (FinFET)Silicon-on-Insulator (SOI)Bulk Complementary Metal Oxide Semiconductor (CMOS)Nanosheet FET (NSHFET)Nanowire FET (NWFET)Gate-All-Around (GAA)Fin WidthGate LengthSilicide BlockingStrain EngineeringThreshold VoltageSelf-HeatingDevice ScalingAdvanced CMOS Nodes.
Information
- Type
- Chapter
- Information
- High Current ESDPhysics and Design, pp. 259 - 300Publisher: Cambridge University PressPrint publication year: 2026
References
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