Introduction

A brief overview and selected topics on DC and thermal compact modeling of III–V compound semiconductor transistors are discussed. Specifically, characteristics of field-effect transistors (GaAs MESFET and pseudomorphic HEMT (pHEMT)) and heterojunction bipolar transistors (GaAs and InP HBTs) are presented. Basic DC characteristics of III–V FETs and HBTs are reviewed, and parameter extraction techniques and methods pertinent to compact modeling are shown. Properly extracted parameters, in turn, can be used for process control and optimization by monitoring device characteristics within and across many wafers. Thermal modeling pertinent to compact modeling is also presented with two approaches demonstrated: physics-based and measurement based. Finally, device reliability evaluation is presented as an example where both DC parameters and thermal modeling are extensively utilized.

The DC model serves as a foundation for any compact model. In the most fundamental sense, DC simulation results based on an accurate model provide detailed bias point information for circuits such as current density, output voltage, and power dissipation to enable robust and well-optimized circuit designs. Furthermore, the DC model serves as the foundation for RF characteristics such as S-parameters. For example in an HBT, S11 and S21 at low frequencies are related to the small-signal model parameters rπ and gm, respectively.