N-type InGaAs MOSFETs

InGaAs and InAs have been used for many years for high-speed and high-frequency electronic devices, in particular as high-electron-mobility transistors (HEMTs), in which modulation doping in a heterostructure is exploited to achieve high electron mobility.^{Reference Kim and del Alamo21} Mature HEMT technology intrinsically suffers from high gate leakage and is thus not the best option for highly scaled devices such as MOSFETs.^{Reference del Alamo22} However, it has acted as an excellent model system in demonstrating the superior properties of III–Vs and thus has helped to push the development of III–V CMOS technology.

Figure 2 shows the remarkable recent progress achieved for InGaAs MOSFETs (with the InAs composition anywhere between 0 and 1) by contrasting it with the relatively well-established InGaAs HEMTs.^{Reference del Alamo, Antoniadis, Guo, Kim, Kim, Lin, Lu, Vardi and Zhao23} InGaAs MOSFETs have now matched the highest transconductance, g _m (g _m= dI _D/dV _GS at constant V _DS with drain current, I _D, source-gate voltage, V _GS, and source-drain voltage, V _DS) ever obtained in HEMTs (Figure 2a).^{Reference Chang, Li, Oxland, Wang, Wang, Contreras-Guerrero, Bhuwalka, Doornbos, Vasen, Holland, Vellianitis, van Dal, Duriez, Edirisooriya, Rojas-Ramirez, Ramvall, Thoms, Peralagu, Hsieh, Chang, Yin, Lind, Wernersson, Droopad, Thayne, Passlack and Diaz24–Reference Kim, Brar and del Alamo26} Crucial for this were significant improvements made in two critical areas of InGaAs MOSFETs: the gate stack and the parasitic resistance. Regarding the gate stack, the excellent scalability of the gate oxide thickness has greatly boosted channel charge control by the gate. The parasitic resistance, on the other hand, consists of contact resistance, source-drain extension resistance, and heterojunction barrier resistance. It is this last component that is greatly improved in MOSFETs with respect to HEMTs. In fact, InGaAs MOSFETs today show a smaller ON-resistance than HEMTs (Figure 2b). In spite of this impressive recent progress, a logic InGaAs MOSFET technology ready for insertion into a sub-10-nm CMOS node still needs significant improvements in the gate stack and the parasitic resistances and faces numerous challenges with the integration of III–V on Si.

Figure 2.

Performance comparison of inversion-type InGaAs metal oxide semiconductor field-effect transistors (MOSFETs) and high-electron-mobility transistors (HEMTs) (with In_xGa_1–xAs composition between x = 0 and 1) versus year: (a) transconductance g _m and (b) ON-resistance R _on. The transconductance of InGaAs MOSFETs has been significantly improved over the last years and is now on par with the highest values of HEMTs. Similarly, the R _on of InGaAs MOSFETs has been dramatically reduced, reaching values of even below the R _on of HEMTs. Reproduced with permission from Reference 23. © 2013 IEEE.

The dielectric/III–V semiconductor interface

The core of a MOSFET is the gate stack, which is of utmost significance to the device performance. The gate stack is composed of a metal gate and a high-κ dielectric barrier on top of the semiconductor channel, and its quality is crucial for effectively modulating the electrostatic potential inside the semiconductor.^{Reference Taur and Ning27} Achieving a high-quality gate stack requires a high-permittivity dielectric free of trapped charges and other defects that is appropriately scaled in layer thickness, possesses a smooth oxide–semiconductor interface with few interfacial imperfections, and has high thermal stability. For the electrical characteristics of III–V MOSFETs, the interface state density, D _it, and the equivalent oxide thickness (EOT or equivalent thickness of SiO₂ that has the same capacitance per unit area) are particularly important.^{Reference Nicollian and Brews28} Interface states are electronic states at the semiconductor/dielectric interface occurring because of non-ideal bonding between the two. They can shift the threshold voltage, degrade the channel mobility, increase the subthreshold swing and thus reduce I _on for a given I _off, and also be a source of instability.^{Reference Taur and Ning27} For high-performance scaled MOSFETs, the gate dielectric has to be appropriately scaled with an EOT far below 1 nm to achieve strong electrostatic gate coupling.

Whereas the development of Si technology has had the advantage of its native oxide SiO₂, the native oxides of III–V materials easily result in Fermi-level pinning,^{Reference Hong, Kwo, Lin and Huang29} and thus the gate is unable to control the channel charge. This was the reason why III–V MOSFETs did not progress in performance for a long time. Early discoveries toward unpinning the Fermi level were based on the in situ deposition of oxides such as Ga₂O₃(Gd₂O₃) [GGO]^{Reference Hong, Passlack, Mannaerts, Kwo, Chu, Moriya, Hou and Fratello30,Reference Hong, Lu, Kwo, Kortan, Mannaerts, Krajewski, Hsieh, Chou and Cheng31} and Gd₂O₃^{Reference Hong, Kwo, Kortan, Mannaerts and Sergent32} on GaAs. Tremendous progress has been achieved in the past few years in preparing and understanding dielectric/III–V interfaces electronically^{Reference Pi, Lin, Chiang, Liu, Chang, Lin, Wertheim, Kwo and Hong33} and electrically.^{Reference Lin, Chiu, Chiang, Lin, Chang, Chang, Chang, Wang, Dekoster, Hoffmann, Hong and Kwo34,Reference Brammertz, Martens, Sioncke, Delabie, Caymax, Meuris and Heyns35} Perfecting the high-κ dielectric/III–V interfaces to lower the D _it and to improve the thermal stability at high temperatures has resulted in improved device performance.^{Reference Ren, Hong, Hobson, Kuo, Lothian, Mannaerts, Kwo, Chen and Cho36–Reference Lin, Chang, Chu, Chang, Chang, Lee, Hong, Chen, Kwo and Hong39} An important breakthrough was achieved by introducing atomic layer deposition (ALD) to fabricate a decent quality gate stack on GaAs.^{Reference Ye, Wilk, Yang, Kwo, Chu, Nakahara, Gossmann, Mannaerts, Hong, Ng and Bude40,Reference Ye, Wilk, Kwo, Yang, Gossmann, Frei, Chu, Mannaerts, Sergent, Hong, Ng and Bude41} This result was unexpected because of the ex situ fabrication of the oxide typically yielding a low-quality interface oxide. This was explained by a “self-cleaning effect” in which the native surface oxides are largely eliminated during the early stages of the ALD process.^{Reference Frank, Wilk, Starodub, Gustafsson, Garfunkel, Chabal, Grazul and Muller42–Reference Hinkle, Sonnet, Vogel, McDonnell, Hughes, Milojevic, Lee, Aguirre-Tostado, Choi, Kim, Kim and Wallace45} Further investigations have been performed to use dielectrics prepared by ALD on various other III–V materials such as InGaAs,^{Reference Xuan, Wu, Lin, Shen and Ye46,Reference Xuan, Lin, Ye and Wilk47} InAs,^{Reference Li, Harmon, Hyland, Salzman, Ma, Xuan and Ye48} and InP.^{Reference Wu, Xuan and Ye49}

Today, the focus is on investigating the possibility of using ALD-deposited high-κ dielectric layers such as Al₂O₃ and HfO₂ and a bilayer of both in InGaAs-based MOSFETs. Interfacial defects, such as As-As dimers and also Ga and As dangling bonds, contribute to the interface state density, which deteriorate device performance.^{Reference Robertson and Falabretti50} Various approaches to optimizing and engineering the gate stack through pre-deposition cleaning treatments,^{Reference Trinh, Chang, Wu, Wong, Chang, Hsieh, Yu, Nguyen, Lin, Lin and Hudait51,Reference O’Connor, Brennan, Djara, Cherkaoui, Monaghan, Newcomb, Contreras, Milojevic, Hughes, Pemble, Wallace and Hurley52} the use of interfacial layers,^{Reference Ok, Lee, Oktyabrsky and Ye53,Reference Wu, Lin, Chiang, Chang, Chiu, Lee, Hong, Lin and Kwo54} modifications of the deposition chemistry,^{Reference Cheng, Apostolopoulos and Fitzgerald55} post-deposition treatments,^{Reference Trinh, Chang, Wu, Wong, Chang, Hsieh, Yu, Nguyen, Lin, Lin and Hudait51,Reference Chen, Zhao, Wang, Xue, Zhou and Lee56,Reference El Kazzi, Czornomaz, Rossel, Gerl, Caimi, Siegwart, Fompeyrine and Marchiori57} and in situ ALD^{Reference Lin, Chang, Lin, Huang, Lee, Kwo and Hong58} are being investigated. For InGaAs, it has been observed that the MOSFET characteristics improved significantly with increasing indium molar fraction.^{Reference Ye, Wilk, Yang, Kwo, Chu, Nakahara, Gossmann, Mannaerts, Hong, Ng and Bude40} Another approach using InP as a barrier layer, in what is known as a “buried-channel” design, has also yielded good MOSFET performance, but is limited in terms of EOT scalability.^{Reference Radosavljevic, Chu-Kung, Corcoran, Dewey, Hudait, Fastenau, Kavalieros, Liu, Lubyshev, Metz, Millard, Mukherjee, Rachmady, Shah and Chau59} A further challenge is to maintain the high electron mobility of InGaAs in MOS structures with scaled gate stacks because of Coulomb scattering, interface roughness scattering, and remote phonon scattering, which can severely degrade the mobility.^{Reference Sonnet, Galatage, Hurley, Pelucchi, Thomas, Gocalinska, Huang, Goel, Bersuker, Kirk, Hinkle, Wallace and Vogel60,Reference Sonnet, Galatage, Hurley, Pelucchi, Thomas, Gocalinska, Huang, Goel, Bersuker, Kirk, Hinkle and Vogel61}

Parasitic resistance

Another challenge to further improve MOSFET performance is posed by parasitic resistances. As shown in Figure 2b, a significant reduction in the ON-resistance, R _on, has already been demonstrated as compared to HEMTs; however, further progress is needed to achieve the parasitic resistance required for ultra-scaled III–V MOSFETs at the contact dimensions allowed for sub-10-nm CMOS nodes. Thus, it is crucial to achieve extremely small metal contact resistance in nanometer-scale contacts. Thanks to the Fermi level pinning location close to the conduction band edge of InGaAs, with an InAs composition of around 70%, very good contacts with small contact resistances have been demonstrated with a variety of metals (Figure 3a).^{Reference Lu, Guo, Vardi and del Alamo62–Reference Law, Carter, Lee, Gossard and Rodwell68} A contact-first approach, in which the first step in the fabrication process consists of Mo deposition, recently yielded contact resistances below 7 Ω.µm for long contacts (longer than 200 nm) and around 40 Ω.µm for contacts as short as 20 nm.^{Reference Lu, Guo, Vardi and del Alamo62} Silicide-like contacts based on Ni, Co, or Pd that is alloyed with InGaAs at relatively low temperatures are also being investigated.^{Reference Kim, Yokoyama, Taoka, Iida, Lee, Nakane, Urabe, Miyata, Yasuda, Yamada, Fukuhara, Hata, Takenaka and Takagi69,Reference Ivana, Kong, Subramanian, Zhou, Pan and Yeo70} Although very promising for device integration, this approach is currently yielding inferior contact resistance values.

Figure 3.

Planar III–V metal oxide semiconductor field-effect transistors (MOSFETs). (a) Contact resistivity of refractory metals on InGaAs versus electron concentration.^{Reference Lu, Guo, Vardi and del Alamo62–Reference Law, Carter, Lee, Gossard and Rodwell68} The different color codes for the various compositions of In_xGa_1–xAs range from x = 0.53 to x = 1 (pure InAs). For reference, typical contact resistivities of metals on n ⁺-Si are also shown. Contacts to n ⁺-InGaAs are as good as, if not better than, those of n ⁺-Si. Increasing the InAs composition results in better contact resistance. (b) Transmission electron micrograph cross-section and schematics of a 20-nm-gate-length gate-last self-aligned InGaAs MOSFET. The channel includes a thin core layer of InAs and two cladding layers of In_0.7Ga_0.3As. The MOS gate structure is in the middle of the figure and consists of Mo gate metal and HfO₂ as gate dielectric. The source and drain contacts are placed on both sides of the gate and self-aligned to it. They consist of a Mo/W bilayer on top of a recessed n ⁺-InGaAs cap. This is one of the smallest and most compact working InGaAs MOSFETs demonstrated.^{Reference Lin, Zhao, Yu, Antoniadis and del Alamo25} (c) ON-current I _on for fixed OFF-current I _off = 100 nA/μm and source-drain voltage V _DS = 0.5 V, as a function of gate length, L _g for state-of-the-art InGaAs MOSFETs. The blue squares denote planar MOSFETs. The red triangles denote tri-gate MOSFETs. For reference, InGaAs high-electron-mobility transistors (HEMTs) are also shown (green diamonds). The green line is a trend line for HEMTs. The blue line represents the highest performance attained by MOSFETs of any kind. MOSFETs have yet to achieve the performance demonstrated by HEMTs. Also, planar MOSFETs seem to face a scaling limit of about 50 nm in gate length, beyond which the performance drastically drops. The data are taken from Reference 25 and references therein.

In addition to the contact resistance, the design of the access region from the source to the channel is crucial for reducing the total parasitic resistance. In that regard, a self-aligned architecture is preferred, where ohmic contacts are very closely spaced from the gate and thus possess low resistance. Gate-first^{Reference Kim, Yokoyama, Taoka, Iida, Lee, Nakane, Urabe, Miyata, Yasuda, Yamada, Fukuhara, Hata, Takenaka and Takagi71,Reference Czornomaz, El Kazzi, Hopstaken, Caimi, Mächler, Rossel, Bjoerk, Marchiori, Siegwart and Fompeyrine72} as well as gate-last^{Reference Lin, Zhao, Yu, Antoniadis and del Alamo25,Reference Egard, Ohlsson, Arlelid, Persson, Borg, Lenrick, Wallenberg, Lind and Wernersson73} III–V MOSFET process flows using precision etching or applying regrown and in situ-doped source/drain regions have been introduced that provide reduced access resistance and help improve the drive current and transconductance. Self-aligned InGaAs MOSFETs with gate lengths as short as 20 nm have been demonstrated (Figure 3b).^{Reference Lin, Zhao, Yu, Antoniadis and del Alamo25}

Integration of III–V semiconductors on silicon

The best integration approach for III–V MOSFETs on Si is still not established and is one of the major challenges. A significant complication is that economic reasons dictate the use of Si as substrate material. A second problem is that a high-performance p-channel device, as required in CMOS, will have to be based on semiconductors with high hole mobility, such as Ge^{Reference Hock, Hackbarth, Erben, Kohn and Konig14,Reference Gupta, Gong, Zhang, Yeo, Takagi and Saraswat74} or InGaSb.^{Reference Oktyabrsky75} Both have different relaxed lattice constants from InAs-rich InGaAs, which renders the combined integration on Si a very difficult technological problem. Several integration schemes are being pursued, such as direct wafer bonding,^{Reference Yokoyama, Kim, Zhang, Taoka, Urabe, Maeda, Takagi, Yasuda, Yamada, Ichikawa, Fukuhara, Hata, Sugiyama, Nakano, Takenaka and Takagi76,Reference Czornomaz, Daix, Caimi, Sousa, Erni, Rossell, El-Kazzi, Rossel, Marchiori, Uccelli, Richter, Siegwart and Fompeyrine77} epitaxial layer transfer to a silicon on insulator substrate,^{Reference Nah, Fang, Wang, Takei, Lee, Plis, Krishna and Javey78} and aspect ratio trapping (ART).^{Reference Fiorenza, Park, Hydrick, Li, Li, Curtin, Carroll and Lochtefeld79} The first approach relies on the transfer of a thin III–V layer onto a thin dielectric on top of the Si wafer (Figure 4a). Instead, the ART process (Figure 4b) is based on the selective growth of lattice-mismatched material inside trenches with high aspect ratios. Threading dislocations are diverted to the sidewalls, and thus high-quality III–V layers at the top of the trench are possible. Efforts have been undertaken to build InGaAs MOSFETs based on this approach.^{Reference Waldron, Wang, Nguyen, Orzali, Merckling, Brammertz, Ong, Winderickx, Hellings, Eneman, Caymax, Meuris, Horiguchi and Thean80} While simple n- and p-channel FETs have been successfully integrated using some of these approaches,^{Reference Yokoyama, Kim, Zhang, Taoka, Urabe, Maeda, Takagi, Yasuda, Yamada, Ichikawa, Fukuhara, Hata, Sugiyama, Nakano, Takenaka and Takagi76–Reference Nah, Fang, Wang, Takei, Lee, Plis, Krishna and Javey78} high-performance transistor demonstrations using any of these techniques are still lacking.

Figure 4.

Integration of III–V semiconductors on silicon. (a) Process flow of the direct wafer bonding technique of thin III–V layers such as InGaAs on insulator on silicon. In this approach, heteroepitaxy using thick buffer layers is applied to achieve high-quality III–V layers on large Si substrates. The InGaAs layer is then transferred onto the target Si wafer by bonding to the buried oxide (BOX). In the next step, the bonding wafer is released and can be reused for growth. The high-resolution transmission electron micrograph (HR-TEM) shows a bonded InGaAs/InAlAs layer with ideal crystallinity on top of the BOX and covered with a thin high-κ gate dielectric material.^{Reference Czornomaz, Daix, Caimi, Sousa, Erni, Rossell, El-Kazzi, Rossel, Marchiori, Uccelli, Richter, Siegwart and Fompeyrine77} (b) Schematics of the aspect ratio trapping technique before and after III–V layer growth. In this approach, high aspect ratio SiO₂ trenches are fabricated on Si substrates. Threading dislocations and stacking faults caused by the growth of lattice mismatched III–V materials on Si are diverted to the sidewalls, resulting in high-quality III–V layers at the top of the trench. (c) Schematics of a grown III–V nanowire on Si with the vapor-liquid-solid (VLS) technique^{Reference Wagner and Ellis87} and nanowire selective-area epitaxy (NW-SAE).^{Reference Björk, Schmid, Breslin, Gignac and Riel135} The scanning electron micrograph shows InAs grown via NW-SAE on Si, and the HR-TEM image shows the resulting high-quality Si/InAs heterointerface. (d) In the template-assisted growth technique, nanotube templates of oxide are fabricated on Si substrates and filled by selective epitaxy with III–V material.^{Reference Das Kanungo, Schmid, Björk, Gignac, Breslin, Bruley, Bessire and Riel89} With this technique, very thin nanowires can be grown.^{Reference Borg, Schmid, Moselund, Signorello, Gignac, Bruley, Breslin, Das Kanungo, Werner and Riel90}

An approach to completely avoid threading dislocations is to limit the extent of the Si/III–V cross-section in two dimensions. Thus, high-quality III–V materials directly on Si can be achieved by the epitaxial growth of NWs (typical diameter <100 nm) (Figure 4c).^{Reference Tomioka, Motohisa, Hara and Fukui81–Reference Hertenberger, Rudolph, Bichler, Finley, Abstreiter and Koblmuller84} If the diameter is made sufficiently small, dislocation formation can be completely avoided, as demonstrated in the Si/GaAsSb and Si/GaAs systems.^{Reference Conesa-Boj, Kriegner, Han, Plissard, Wallart, Stangl, Fontcuberta i Morral and Caroff85,Reference Tomioka, Yoshimura and Fukui86} Among the common methods to form III–V NWs on Si is the vapor-liquid-solid (VLS) method, in which a nanoparticle is used to collect growth material and enhance the epitaxial growth rate underneath it.^{Reference Wagner and Ellis87} The particle thus resides on top of the NW, while the NW grows upward, in most cases along the [111]B direction.^{Reference Tomioka, Motohisa, Hara and Fukui81,Reference Johansson, Wacaser, Dick and Seifert88}

NW selective-area epitaxy (NW-SAE) seems a more promising approach for III–V integration on Si because it avoids the use of a catalyst nanoparticle, and instead uses a patterned oxide mask to control the location of III–V growth.^{Reference Tomioka, Motohisa, Hara and Fukui81} The disadvantage of these techniques is that they rely on Si(111) substrates to grow NWs in that direction. Recently, a template-assisted growth technique has been introduced that overcomes various NW growth limitations (Figure 4d).^{Reference Das Kanungo, Schmid, Björk, Gignac, Breslin, Bruley, Bessire and Riel89} With this technique, epitaxial growth of III–V homo- and heterostructure NWs on various directions, including Si (100) and scaled NWs with a 25 nm diameter, have been demonstrated.^{Reference Borg, Schmid, Moselund, Signorello, Gignac, Bruley, Breslin, Das Kanungo, Werner and Riel90} Although these wires have a very high potential for future III–V device integration on Si, the vertical device processing is more challenging.