Load impedance variations at intrinsic planes

We will extend the previous analysis to the case of mismatched load impedance. Z _load is now modified such that Z _load = 50 ζ _load [Ω]; with ζ _load = (r + jx) being the normalized mismatched load impedance. Four typical cases will be studied, namely:

(15)$$\eqalign{Z_{re + } = & \,50\lpar {1\comma \;5 + jO} \rpar \lsqb {\rm \Omega } \rsqb \cr Z_{re-} = & \,50\lpar {0\comma \;667 + jO} \rpar \lsqb {\rm \Omega } \rsqb \cr Z_{im + } = & \,50\lpar {1 + jO\comma \;408} \rpar \lsqb {\rm \Omega } \rsqb \cr Z_{im-} = & \,50\lpar {1-jO\comma \;408} \rpar \lsqb {\rm \Omega } \rsqb } . $$

These load impedances are located in a constant 1.5-VSWR locus, as illustrated in Fig. 6, and correspond to a mismatched environment that can occur in AESA applications.

Fig. 6.

Studied Z _load (constant 1.5-VSWR) in DPA realistic mismatched configuration.

The relationship between voltages and currents is given by

(16)$$\left({\matrix{ {V_{main}} \cr {I_{main}} \cr } } \right) = \left({\matrix{ {-j\lpar {1 + n} \rpar \zeta_{load}} & {-jR_{opt}} \cr {\displaystyle{{-j} \over {R_{opt}}}} & 0 \cr } } \right)\left({\matrix{ {V_{aux}} \cr {-I_{aux}} \cr } } \right)\comma \;$$

V _main and V _aux are plotted in Fig. 7, along with associated load impedance variations in Fig. 8, for the four mismatched load conditions, and for the same optimum drives as derived in the 50-Ω nominal case. For the sake of clarity, arg(V _aux) is not reported, because it remains in quadrature with a ₁, and is not altered by the mismatch effect, as described in the section Theoretical assumptions.

(17)$$\eqalign{V_{main} = & \,V_{DD}\lpar {a_1\lpar {1 + n} \rpar \zeta_{load} + jn\;a_2e^{\,j\Phi }} \rpar \cr V_{aux} = & \,jV_{DD}a_1} . $$

Fig. 7.

V _main and V _aux variations versus a ₁ in mismatched load configuration.

Fig. 8.

Impedance trajectories at intrinsic planes of Main and Auxiliary devices; the Main impedance is modulated from (1 + n)ζ _loadR _opt (back-off operation) to (1 + n)ζ _loadR _opt − nR _opt (saturated power condition), Auxiliary impedance is modulated from Open Circuit (O.C) to R _opt/n.

When the 50 ohms matched-configuration optimum RF drives are maintained (e.g. because of a fixed splitting configuration), efficiency and linearity performances of the DPA are strongly affected.

When a resistive load-pull occurs (Z _load = Z _re+), V _main can reach higher values than V _DD, potentially strongly affecting the linearity of a real-life DPA and even causing reliability issues to the Main device. When Z _load = Z _re−, V _main is always lower than V _DD, reducing the net active power delivered to the load, and impacting the overall efficiency of the DPA.

When a reactive load-pull effect occurs (Z _load = Z _im− or Z _im+), V _main is no longer in phase with I _main, and has magnitude higher than V _DD above the threshold point a _1th, both contributing to produce a constant net active main power, and thus do not impact the global efficiency of the DPA. The active powers injected by the Main and Auxiliary devices are given by:

(18)$$\eqalign{P_{main} = & \,\displaystyle{1 \over 2}real\lpar {V_{main}I_{main}^\ast } \rpar \cr = & \,\displaystyle{1 \over 8}a_1^2 R_{opt}\lpar {1 + n} \rpar aI_{max}^2 \;\;\;\cr & \;-\displaystyle{1 \over 8}nR_{opt}I_{max}^2 a_1\;a_2\sin \lpar \Phi \rpar \;\;\cr P_{aux} = & \,\displaystyle{1 \over 2}real\lpar {V_{aux}I_{aux}^\ast } \rpar \cr = & \,\displaystyle{1 \over 8}nR_{opt}I_{max}^2 a_1\;a_2\sin \lpar \Phi \rpar}\!\!\!\!. $$

The active powers delivered by both transistors sum up to give the active power transferred to the load, which is independent of the Φ value and is a function of the real part of the mismatched normalized load impedance. The resulting efficiency function is given in (19) and is plotted in Fig. 9.

(19)$$Eff\lpar {a_1\comma \;a_2} \rpar \;\lpar \% \rpar = \displaystyle{{P_{main} + P_{aux}} \over {P_{DCmain} + P_{DCaux}}} = \displaystyle{\pi \over 4}\displaystyle{{\lpar {1 + n} \rpar a_1^2 } \over {a_1 + na_2}}\;r. $$

Fig. 9.

Drain efficiency performances of the DPA when load-pull occurs at the output plane; !! annotation means that electrical constraints are not satisfied (e.g. |V _main| > V _DD).

DPA performances with optimal-efficiency RF drives

The new maximum-efficiency driving conditions are sketched in the Fresnel representation of the voltage vectors V _main and V _aux. As it can be seen in Fig. 10, they are dependent on the load-pull presented at the output of the DPA structure. Again, to ensure maximum-efficiency operation, the auxiliary transistor is off in the 0 ≤ a ₁ ≤ a _1th range, with:

(20)$$a_{\;1th} = \displaystyle{{1\;} \over {\lpar {1 + n} \rpar \vert {\zeta_{load}} \vert }}. $$

Fig. 10.

Fresnel representation of the fundamental voltages V _main and V _aux for load mismatch conditions.

For a ₁ = a _1th, the produced complex main voltage is:

(21)$$V_{main\_th} = V_{DD}\displaystyle{{\zeta _{load}} \over {\vert {\zeta_{load}} \vert }}. $$

In the $a_{1\_th} \le a_1 \le 1$ range, the auxiliary device comes into play to modulate the complex impedance presented to the main transistor, producing an out-of-phase drain-to-source voltage with a constant V _DD magnitude. The corresponding optimal efficiency drive is thus given by:

(22)$$a_2e^{\,j\Phi } = j\displaystyle{1 \over n}\zeta _{load}\left({a_1\lpar {1 + n} \rpar -\displaystyle{1 \over {\vert \zeta_{load}\vert }}} \right)\comma \;$$

which can be written in polar form as:

(23)$$\eqalign{\vert {a_2} \vert = & \displaystyle{1 \over n}\lpar {a_1\lpar {1 + n} \rpar \vert \zeta_{load}\vert -1} \rpar \cr {\rm \Phi } = & -\arctan \left({\displaystyle{r \over x}} \right)-\pi } . $$

It can be inferred that when load-pull occurs such that |ζ _load| > 1, the optimum drive implies |a ₂| > 1 at full RF power in order to maintain the |V _main| = V _DD condition. For this purpose, a larger auxiliary device should be used, even in a symmetrical DPA topology. The DPA optimum RF drives associated with the four impedance configurations are represented in Fig. 11. As shown in Fig. 12, associated optimal impedance loci move along constant Q trajectories, depending on the load mismatch (with Q = x/r).

Fig. 11.

RF drives for optimal efficiency of DPA (n = 1) for the studied mismatched loads.

Fig. 12.

Impedance trajectories when optimal RF driving conditions for maximum efficiency are applied (illustrated here for n = 1): Main impedance is modulated from (1 + n)ζ _loadR _opt (back-off operation) to R _opt ζ _load/|ζ _load|(saturated power condition), Aux. impedance is modulated from Open Circuit (O.C) to R _opt/ζ _load(1 + n − 1/|ζ _load|).

When optimum RF drives a ₁, a ₂, and Φ are applied, maximum efficiency is recovered, taking into account the physical constraints of sustainable voltages V _main and V _aux. The optimal efficiency function is represented in Fig. 13 for the four cases of interest. The ratio κ _Eff between the efficiency for 50 Ω load (ζ _load = 1)) and the efficiency for the mismatched load (ζ _load ≠ 1) with optimal RF drives at a ₁ = a _1th (at turn-on point) is:

(24)$$\kappa _{Eff} = \displaystyle{{Eff_{\zeta _{load}\ne 1\comma \;\;with\;opt\;drives}} \over {Eff_{\zeta _{load} = 1}}} = \displaystyle{r \over {\vert {\zeta_{load}} \vert }}. $$

Fig. 13.

DPA efficiency performances when optimal RF drives are applied for the studied mismatched load.

The corresponding auxiliary turn-on point shift is:

(25)$$\kappa _{a_{1th}} = \displaystyle{{a_{1th}{\zeta _{load}\ne 1\comma \;\;with\;opt\;drives} } \over {a_{1th}{\zeta _{load} = 1} }} = \displaystyle{1 \over {\vert {\zeta_{load}} \vert }}. $$

These quantities are synthesized in Table 1. Non-physical results (e.g. when associated electrical constraints are not satisfied) are annotated with !!. For example, from Table 1 it is not possible to ensure the same maximum DPA efficiency of 78.5% when resistive load-pull occurs, with a shift of the turn-on point. On the contrary, it is not possible to maintain maximum efficiency performances while fulfilling the device's constraints when reactive output load-pull exists.

Table 1.

DPA performances with and without optimal drives in mismatched environment. (!!) is put when circuit constraints are not satisfied.

DPA prototype performances under matched-load configuration

A 20 W, C-band, dual-input symmetrical DPA prototype has been built to validate the proposed theoretical study. Commercially available Wolfspeed GaN HEMT packaged components [13] and nonlinear transistor model have been used in HB simulation in Keysight ADS CAD environment. The layout of the final prototype is presented in Fig. 14.

Fig. 14.

Layout of the symmetrical dual-input GaN DPA prototype.

An optimum intrinsic load R _opt of 34 Ω at 41 dBm output power has been determined. Large-signal simulated performances of the DPA are presented in Fig. 15, at a center frequency of 3.9 GHz. Main and Auxiliary gate to source bias voltages has been adjusted to ensure the correct DPA behavior in nominal 50 Ω loading condition (V _GGmain = −3V and V _GGaux = −6V).

Fig. 15.

DPA prototype simulation results at center frequency of 3.9 GHz in the nominal case (Z _load = 50Ω).

We define the power and phase RF imbalances between Auxiliary and Main devices as ΔP and ΔΦ, respectively, as:

(26)$$\eqalign{\Delta P = & \;P_{aux}-P_{main} \cr \Delta \Phi = & \;\Phi _{aux}-\Phi _{main}} $$

In this case, optimum power and phase driving offsets (ΔP = 0dB and ΔΦ = 80°) are in good agreement with expected theoretical values in the section Dual-input DPA theoretical behavior under mismatched load. In the following, current and voltage quantities at the fundamental frequency will be analyzed and all phases will be referenced to I _Main, resulting phasors are denoted with the N subscript.

Load modulation effect is clearly observed, as the intrinsic Main device impedance is modulated from 59 Ω to 34 Ω, following a real-to-real impedance locus. Meanwhile, intrinsic Auxiliary device impedance is modulated from open circuit condition to 34 Ω. It can be shown in Fig. 15 (top left) that the Main device is effectively kept saturated in the load-modulation region, giving back-off efficiency improvements as it can be seen in Fig. 15 (bottom left).

DPA prototype performances under output mismatch configuration

The same load mismatch conditions studied in the theoretical section have been applied to the prototype DPA. First, the static CW optimum matched-case splitting conditions (ΔP = 0dB and ΔΦ = 80°) are maintained. Associated modified load impedance variations are reported on Fig. 16, and are in good agreement with theoretical trends shown in the section Dual-input DPA theoretical behavior under mismatched load.

Fig. 16.

Distorted intrinsic Main and Auxiliary impedances in mismatched load configuration.

Associated intrinsic voltages and currents are plotted in Fig. 17, to illustrate how mismatch conditions can adversely affect the DPA behavior. As predicted in the theoretical section, it can be clearly confirmed in Figs 16 and 17 that, as the output impedance is shifted from low value to high value along the resistive part (i.e. for Z _re− and Z _re+ loading conditions, respectively), the net fundamental voltage produced across the main transistor increases.

Fig. 17.

Voltages produced across Main and Auxiliary devices. Reference 50 Ω case is plotted for comparison.

This could potentially induce reliability and linearity issues in the DPA structure. In our case, thanks to the inverse class-F operation employed in the proposed design the net value of the fundamental frequency component of the drain voltage can reach higher values than the theoretical limit of 28 V (i.e in the order of 34 V).

When a reactive load-pull effect occurs (i.e. for Z _load = Z _im− or Z _im+), the Main device impedance is shifted along a constant reactance locus, as theoretically predicted in Fig. 8. In this case, V _main is no longer in phase with I _main. Its phase depends on the RF drive level, while its magnitude is always higher than its nominal V _DD − V _k value in the load-modulation range, causing linearity and reliability issues in the DPA structure. Drain efficiency profiles are plotted in Fig. 18 for the four tested impedances. It is verified that, in this typical case, DPA efficiency is strongly impacted in the case of a resistive load pull, and is only slightly dependent on a reactive load pull.

Fig. 18.

DPA simulated PAE performances for mismatched load impedances.

Optimum input splitting parameters ΔP and ΔΦ have then been applied to mitigate efficiency power performance decrease. ΔP and ΔΦ are derived according to the procedure described in the section Dual-input DPA theoretical behavior under mismatched load, so that:

• • Fundamental voltage produced across intrinsic Main device is restricted by the V _DD − V _k = 30 V, defined as a target value, so as to ensure optimum safe saturated conditions of devices

• • Associated impedance Z _Main is modulated along a constant Q trajectory. Q is defined according to the output load mismatch, as x/r.

Optimum Main and Auxiliary currents and intrinsic load impedances are plotted in Figs 19 and 20. They are consistent with theoretical profiles, as it is confirmed that:

1. (i) A resistive load-pull (Figs 19 and 20, top and bottom left), implies an Auxiliary device turn-on point shift and a maximum available current quantity modification, with no modification on the phase

2. (ii) A reactive load-pull (Figs 19 and 20, top and bottom right) implies only a phase shift.

Fig. 19.

Optimum dual-input DPA prototype fundamental current profiles. Reference 50 Ω case is indicated for comparison.

Fig. 20.

Impedance trajectories at intrinsic planes of Main and Auxiliary devices when optimal RF driving conditions are applied.

It is worth noting that, to ensure a constant Q value, ΔΦ has to be slightly modified versus the RF level, which is not predicted in the theoretical section. This is mainly to compensate for the difference of nonlinear AM-to-PM conversions of the devices.

Associated voltages produced across the Main and Auxiliary devices are plotted in Fig. 21. It is verified that a constant fundamental magnitude voltage of V _DD − V _k = 30 V is maintained for the Main transistor within the modulation range. Simulated best constrained-efficiency profiles at 3.9-GHz (center frequency) are reported in Fig. 22. For comparison, the efficiency profiles without optimal RF drives have been reported, along with the matched-configuration initial DPA performances. Simulated DPA efficiency performances when the working frequency is varied are reported in Fig. 23 (across 300-MHz of bandwidth, approximately 8% of fractional bandwidth, representing a typical use case). They are obtained while keeping the same (optimal) RF driving conditions, derived at the center frequency. It shows that, although the overall performances of the DPA are subjected to RF deviations, mainly because of the inherent dispersive nature of the output combiner, a quasi-static approach is sufficient for such moderate RF bandwidth.

Fig. 21.

Simulated voltages produced across Main and Auxiliary devices when optimal RF drives are applied.

Fig. 22.

Simulated DPA prototype efficiency at the center frequency of 3.9 GHz, with and without optimal RF drives simulated. Reference 50 Ω case is reported for comparison.

Fig. 23.

DPA efficiency profiles when the frequency is varied ±150 MHz from the central frequency (8% of fractional bandwidth). Reference 50 Ω cases are reported for comparison.

Figure 24 shows the associated intrinsic Main and Auxiliary device load lines at the center frequency and at saturated power condition (around 43dBm of output power), and highlights related large-signal reliability issues. It is of particular interest to note the RF stress reduction of the Main device in Z _re+, Z _im+ and Z _im− mismatched load condition thanks to the application of the appropriate RF drives (implying a larger Auxiliary device in Z _re+ case, as it can be seen on the I-V trajectory, and as predicted in the theoretical section).

Fig. 24.

Simulated intrinsic loadlines of the Main (red circles) and Auxiliary (blue crosses) devices in mismatched environment with and without optimal input RF drives.