Analysis of PD/combiner circuit

The topology of the modified Y-junction PD/combiner circuit is shown in Fig. 1. The circuit consists of three parts: a Y-junction structure based on SIW and two identical two-way HMSIW PDs. The signal through which the Y-junction structure is divided into two paths and then four output ports is achieved by HMSIW dividers. To improve the isolation between the four output ports, the isolation resistors are set between the two adjacent HMSIW. In addition, only a single substrate is used in the PD/combiner circuit; on the one hand, it is easy to install the isolation resistor, and it can improve the reliability of the circuit.

Fig. 1.

Topology of modified four-way Y-junction SIW power divider/combiner circuit.

As can be seen, the modified four-way Y-junction PD/combiner is symmetrical, so the even- and odd-mode equivalent circuit analysis can be used. The equivalent circuit of the circuit is shown in Fig. 2. Under the even-mode excitation, a bisection of the PD is shown in Fig. 2(a). Z ₀ and Z ₁ are the characteristic impedance of microstrip line and SIW. The characteristic impedance of the taper-shaped transition at x can be derived as [Reference Deslandes23]:

(1.a)$$Z_{T(x)} \displaystyle{{120\pi} \over {\sqrt {\varepsilon _e} [(w_1 (x)/d) + 1.393 + 0.677\ln ((w_1 (x)/d) + 1.444)]}},$$

where

(1.b)$$w_1 (x) = \displaystyle{{x(w_4 - w_3 ) + w_3 t_2} \over {t_2}}, $$

d is the height of the substrate; ε _e is the relative permittivity; t ₂ is the length of the taper; w ₃ and w ₄ are the widths of the taper, as shown in Fig. 1. The quarter wavelength taper is sufficient to obtain a good return loss. In any case, taper lengths must be chosen as a multiple of a quarter of a wavelength in order to minimize the return loss. The transmission parameters of a linear tapered TEM transmission line are already known analytically [Reference Lu24] and the widths w ₃ and w ₄ can be achieved. These equations are used to verify the return loss of the taper over the full bandwidth. According to the end of the taper, the reflection coefficient and the input impedance can be derived as:

(2.a)$$\Gamma _{{\rm in}1} = \displaystyle{1 \over 2}\int_0^{t_2} {e^{ - j2\beta x}} \displaystyle{{d[\ln 2Z_T (x)]} \over {dx}}dx + \Gamma _L, $$

(2.b)$$Z_{in1} = \displaystyle{{(1 + \Gamma _{in1} )2Z_1} \over {(1 - \Gamma _{in1} )}}.$$

Fig. 2.

Equivalent circuit model of broadband-modified four-way Y-junction power divider/combiner circuit: (a) even-mode equivalent circuit; (b) odd-mode equivalent circuit.

Thus, the input impedance of the Y-junction Z _in2 and the input impedance Z _ine can be, respectively, derived as:

(3.a)$$Z_{in\,2} = 2Z_1 \displaystyle{{Z_{in1} + 2jZ_1 \tan \theta _1} \over {2Z_1 + jZ_{in\,1} \tan \theta _1}}, $$

(3.b)$$Z_{ine} = \displaystyle{{Z_{in\,2}} \over {1 + jBZ_{in\,2}}}. $$

When part A is matched, the total input impedance of the part A circuit is equal to Z ₁. The good impedance match can be achieved when:

(4)$$B = \displaystyle{1 \over {\,jZ_1}} - \displaystyle{{2Z_1 + jZ_{in1} \tan \theta _1} \over {2jZ_1 (Z_{in1} + 2jZ_1 \tan \theta _1 )}}.$$

When part A is matched, the total input impedance of the part A circuit is equal to Z ₁. The good impedance match can be achieved when:

(5)$$Z_{ine} = Z_1. $$

A centrally located via acts as an inductive matching post to nullify the effect of the Y-junction capacitance and therefore promoting lower return loss at the input. The parameter “w ₂” determines the propagation constant of the fundamental mode, the diameter of via-holes “d”, and the pitch length of via-holes “p” are set to minimize the radiation loss and the return loss. The “d” and “p” can be achieved according to [Reference Deslandes and Wu25] and the dielectric constant in the frequency normalization allows an almost direct design of SIW junctions using any substrate by determining w ₂. The results are valid in the following range [Reference Germain, Deslandes and Wu26]:

(6)$$0.65 \lt w_2 \sqrt {\varepsilon _r} /\lambda \lt 0.92.$$

Furthermore, it can be found from Fig. 2(a) that part A of the even-mode equivalent circuit can be further analyzed by even and odd modes. The even- and odd-mode equivalent circuits of part A are shown in Fig. 3. As we can see from Fig. 3(a), in the even-mode equivalent circuit, no current flows through the isolation resistor. Thus, the input impedance and reflection coefficient, which are seen from the end of the HMSIW, can be derived as:

(7.a)$$Z_{in\,3} = Z_2 \displaystyle{{2Z_1 + jZ_2 \tan \theta _3} \over {Z_2 + 2jZ_1 \tan \theta _3}}, $$

(7.b)$$\Gamma _{in\,3} = \displaystyle{{Z_{in\,3} - Z_{T1} (0)} \over {Z_{in\,3} + Z_{T1} (0)}}.$$

Fig. 3.

Equivalent circuit model of part A: (a) even-mode equivalent circuit of part A; (b) odd-mode equivalent circuit of part A.

The characteristic impedance of the taper-shaped transition at x in the odd-mode equivalent circuit can be derived as [Reference Deslandes23]:

(8.a)$${\rm Z}_{T1} (x) = \displaystyle{{120\pi} \over {\sqrt {\varepsilon _e} [(w_2 (x)/d)\! +\! 1.393 + 0.667\ln ((w_2 (x)/d)\! +\! 1.444)]}},$$

where

(8.b)$$w_2 (x) = \displaystyle{{t_1 w_1 - (w_1 - w_3 )x} \over {t_1}}, $$

t ₁ is the length of the output taper, and w ₁ and w ₃ are the widths of the taper, as shown in Fig. 1. Seen from the end of the taper, the reflection coefficient and the input impedance can be derived as:

(9.a)$$\Gamma _{{\rm in}} = \displaystyle{1 \over 2}\int_0^{t_1} {e^{ - j2\beta x}} \displaystyle{{d[\ln Z_{T1} (x)]} \over {dx}}dx + \Gamma _{{\rm in}3}, $$

(9.b)$$Z_{in} = \displaystyle{{(1 + \Gamma _{in} )Z_0} \over {(1 - \Gamma _{in} )}}.$$

The reflection coefficient at the port 2 can be derived as:

(10)$$\Gamma _0 = \displaystyle{{Z_{in} - Z_0} \over {Z_{in} + Z_0}} = \Gamma _{in}. $$

Therefore, the reflection coefficient of the port 2 can be determined by the above equations, when the port 2 reflection coefficient Γ₀ is given. The parameters of microstrip transition can be obtained [Reference Lu24]. As shown in Fig. 3(b), in order to achieve the impedance match, the circuit must satisfy:

(11.a)$$\displaystyle{{Z_{in\,2} (R/2)} \over {Z_{in\,2} + R/2}} = Z_{T1} (0),$$

where

(11.b)$$Z_{in\,2} = jZ_2 \tan \theta _3. $$

Thus, the isolation resistor must satisfy:

(12.a)$$R = \displaystyle{{2Z_{in\,2} Z_{T1} (0)} \over {Z_{in\,2} - Z_{T1} (0)}},$$

when $\theta _3 = \displaystyle{\pi \over 2},Z_{in2} = \infty $. By equation (12.a), resistor can be expressed as:

(12.b)$$R = 2Z_{T1} (0).$$

The value of isolation resistor can be determined by equation (12.b). After the initial width of the taper w ₁ 1 is determined. The Z _T1(0) and the value of isolation resistor can be determined. The slot can be determined according to [Reference Eom, Byun and Lee27].

The correctness of above deduction can be verified by the simulation results of the circuit. The relationship between resistor and isolation or return loss when w ₁ = 2.5 mm is shown in Fig. 4, when the value of isolation resistor is about 50–60 Ω, the isolation and the VSWR bandwidth are better. When w ₁ = 2.5 mm, the Z _T1 (0) ≈ 28.9 Ω and R = 57.8 Ω. The simulation and measurement results show good agreement. The final value is R = 51 Ω.

Fig. 4.

Effect of isolation resistor on circuit isolation and output VSWR: (a) effect on isolation; (b) effect on output VSWR.

Summary of the total design procedure

1. (a) The width of the 50 Ω transmission line w ₃ can be determined by the theory of transmission lines and the width of the microstrip taper w ₁ and w ₄ can be determined by equations (1) and (8) according to [Reference Deslandes23].

2. (b) The taper lengths t ₁ and t ₂ should be chosen as a multiple of a quarter of a wavelength in order to minimize the return loss. The analytical equations presented in [Reference Lu24] are applied to find the length that minimizes the return loss over the full bandwidth.

3. (c) The diameter of via-holes “d” and the pitch length of via-holes “p” are determined according to [Reference Deslandes and Wu25], and the equivalent width of the SIW w ₂ can be determined by equation (6) and the inductive post can be generated with the use of an FEM software package according to [Reference Germain, Deslandes and Wu26].

4. (d) The gap between the HMSIWs is an important design factor, the length of the gap L ₁, L ₂, and the width of the gap g can be determined according to [Reference Eom, Byun and Lee27] and the resistance can be determined by equation (12)

5. (e) When the initial parameters are obtained according to the aforementioned design procedure, the proposed PD can be constructed and optimized in 3D electromagnetic simulation tools (such as Ansoft-High Frequency Structure Simulator (HFSS)). Then, the optimized structural dimensions can also be obtained.

Simulation and realization of PD/combiner circuit

The broadband-modified four-way Y-junction PD is fabricated with a two-layer substrate Taconic RF-35 with a dielectric constant ε _r of 3.5, a thickness of 0.508 mm, and a loss tangent of 0.0018. Figure 5 gives the fabricated broadband four-way Y-junction PD, and the final optimized circuit size is shown in Table 1.

Fig. 5.

Photograph of the broadband-modified four-way Y-junction power divider/combiner circuit.

Table 1.

Values of parameters of circuit

The simulated and measured results are shown in Fig. 6. It can be seen from Fig. 6(a), the center frequency of the circuit is 5.75 GHz. The simulated input return loss is larger than 15 dB, and the measured one is larger than 17 dB in a frequency range of 4.5–7 GHz. Equal power division for simulated results is achieved around 4.5–7 GHz, while the measured insertion losses are around 1.2 dB, and amplitude unbalance is about ±0.25 dB in the same frequency range. The measured results of phase relationship among output ports are shown in Fig. 6(b); it can be seen that the measured phase unbalances are ±2° from 4.5 to 7 GHz. In addition, the simulation and measured results of the isolation and the output VSWR are shown in Figs 6(c) and 6(d); it can be seen that the isolation of adjacent output ports (such as ports 2, 3 and ports 4, 5) is more than 13 dB. It is better than the non-adjacent ports isolation, which is more than 11 dB across the band 5.2–7 GHz. The better isolation is caused by isolation resistors that are loaded between the adjacent ports. As we can see from Fig. 6(d), the simulation and measured results of the output return loss are both better than 15 dB. The measured results are in good agreement with the simulated ones, and the small difference between the two is mainly caused by the manufactural error. The increase of the insertion loss is mainly caused by the conductor loss of the substrate and the loss of the SMA joint.

Fig. 6.

Simulation and test results of broadband-modified four-way Y-junction power divider/combiner circuit: (a) input return loss and insertion loss; (b) phase; (c) isolation; (d) output return loss.