Coupling

In theory, the farfield radiation pattern of an array of elements can be seen as a lossless combination of each element pattern. In reality, there is mutual coupling between the elements resulting in a change of the boundary conditions, that in turn affects the radiation and terminal properties. Figure 1 shows a case of two antennas forming a 1 × 2 array. To analyze the affect of the mutual coupling, Z-parameters calculations can be used:

(1)$${\bf v} = \left( {\matrix{ {v_1} \cr {v_2} \cr } } \right) = {\bf Z}\cdot {\bf i},$$

(2)$${\left\{ {\matrix{ \matrix{v_1 = Z_{11}i_1 + Z_{12}i_2; \hfill \cr v_2 = Z_{21}i_1 + Z_{22}i_2. \hfill} \cr } } \right.}, $$

(3)$$ v_1 = v_{S1} - Z_{S1}i_1, $$

(4)$$ v_{S1} - Z_{S1}i_1 = Z_{11}i_1 + Z_{12}i_2, $$

(5)$$ i_1 = {\displaystyle {v_{S1} -Z_{12}i_2}\over {Z_{11}+Z_{S1}}}, $$

(6)$$v_2 = \displaystyle{{Z_{21}v_{S1}} \over {\underbrace{{Z_{11} + Z_{S1}}}_{{{v}_{2}^{{oc}} }}}} + \underbrace{{\left[ {Z_{22}-\displaystyle{{Z_{21}Z_{12}} \over {Z_{11} + Z_{S1}}}} \right]}}_{{{\rm }{\rm Z}_{in,2}}}i_2.$$

Fig. 1.

Two elements array coupling diagram.

It can be seen in Equation 6, that the input voltage at port 2 depends on the voltage of port 1. This dependency is translated into input characteristics at port 2 and radiation pattern changes. Let us look at the radiation pattern of this array. The total radiation pattern is the sum of the embedded patterns of each element, while all the other elements are “open circuit”.

(7)$$ f\,(\theta,\phi) = \sum_{n}^{}f_n^{oc}(\theta,\phi)i_n = f_1^{oc}i_1 + f_2^{oc}i_2. $$

To show the impact of the first element on the second element pattern, Equation 5 will be used, with v ₁ = 0.

(8)$$f\,(\theta ,\phi ) = f_2^{oc} i_2-\displaystyle{{\,f_1^{oc} Z_{12}i_2} \over {Z_{11} + Z_{S1}}} = \underbrace{{\left[\,f_2^{oc} -\displaystyle{{Z_{12}} \over {Z_{11} + Z_{S1}}}f_1^{oc} \right]}}_{{{\rm } {f}_{\rm 2}^{{oc}^{\prime}} (\theta ,{\kern 1pt} \phi )}}i_2.$$

In conclusion, the influence of each element on each other should be taken into consideration of the array structure.

Next, to simulate possible coupling in a similar structure of J-Band elements, CST MWS was used. The simulated structure is shown in Figure 2. The element distance of 2 mm was chosen for practical reasons, and its effect will be discussed in the next section. In general, to achieve greater steering angles for phased array, the distance should be smaller than λ, but as distance grows, so does the gain of the array. As for the coupling between the elements, the relation between it and the distance is reversed.

Fig. 2.

Simulated structure of the 1 × 2 array with d = 2 mm.

At f = 264 GHz − Re{Z ₂₁} is at its maximum with 2.4 Ω, while Im{Z ₂₁} reaches its maximum value, 1.67 Ω, at 259.5 GHz. Using Equation 8, Z _source = 50 Ω together with Z ₁₁ and Z ₂₁ values from Figures 3, 4 at f = 264 GHz, yields around ($0.02-0.003j)f^{OC}_1$. It represents the effect of the first element on the radiation pattern of the second element, and will affect both the amplitude and the phase difference between them. It is important to note that for frequency range measured in this paper, simulated coupling between elements is <0.1%.

Fig. 3.

Z ₂₁ real and imaginary parts representing coupling between two J-Band elements of the 1 × 2 array with d = 2 mm.

Fig. 4.

Z ₁₁ real and imaginary parts representing the input impedance of a single J-Band element.

Another way to illustrate coupling affects would be to compare element radiation pattern between a stand alone element and an element in array. Figure 5 demonstrates the difference, and it can be seen that other elements have impact on the phase and amplitude of a single element.

Fig. 5.

Radiation pattern comparison between stand-alone element simulation and single element in an array, f = 280 GHz.

Phase and amplitude mismatch

To analyze the phase and amplitude mismatch impact on the simulation it is necessary to determine the range of possible deviation for each parameter. Phase mismatch can be a product of a small mismatch between the feeding network outputs, through bondwires connected to the chip input pads. This difference is than multiplied by ×27. Coupling effect discussed in the previous subsection could also add to the phase differences. This small error can get as high as ±1.1^° so the maximum phase mismatch between elements can get as high as 60^°. Figure 6 shows simulated E-Plane results for both 0^° and 60^° phase mismatch. It can be seen that the maximum simulated phase mismatch gives 5^° direction shift on E-Plane, also resulting in 0.2 dB mainlobe loss.

Fig. 6.

Phase mismatch impact on the E-Plane of the Farfield Realized Gain of the 1 × 2 array, f = 280 GHz; d = 2 mm.

Regarding the amplitude deviation between array elements, the reason can be different DC operating points for each element, and coupling issues. Amplitude deviation affects the gain of the total radiation pattern and sidelobe level. Figure 7 shows the impact of amplitude mismatch on the radiation pattern. The change can be seen mostly on the sidelobe level, but there is also a small mainlobe decline.

Fig. 7.

Amplitude mismatch impact on the E-Plane of the Farfield Realized Gain of the 1 × 2 array, f = 280 GHz; d = 2 mm.

J-Band array

The starting point of this research was the development of the J-Band radiating source [Reference Jameson and Socher6] and further interest to develop a solution for an array implementation in sub-THz bands. The previous paper showed remarkable results for single chip, with effective isotropically radiated power (EIRP) over 10 dBm and total radiated power (TRP) of 0 dBm with 15 GHz bandwidth. As in the single chip case CST software was used to simulate and estimate the performance of the ring antenna array in the CMOS structure environment. In Figure 8 simulation results are presented to compare the patterns of one versus four elements. Measurements for single chip showed a slight shift from simulation results,  and the maximum gain was achieved for 287 GHz instead of 275 GHz, received in the simulation.

Fig. 8.

Comparison between radiation patterns of a single element and the 1 × 4 array.

Usually, in uniform arrays, the distance between the elements should be λ/2 ≤ d ≤ λ for the energy to be concentrated around the broadside direction. In Figure 9 one can see the gain and the sidelobe suppression level versus element distance. The dependence of the gain on the spacing is also shown in Equation 9. It can be seen that spacing larger than λ causes no increase in gain but a rise in a sidelobe level. Thus, implementing an array with element spacing close to λ ≈ 1 mm is a good point in terms of both array gain and grating lobe suppression. However, as can be seen in Figure 10, DC pads located between the elements placement on the PCB determine the minimum element spacing. Due to manufacturing process constraints on minimum via/metal dimensions, the minimum element spacing of the array is set to 2 mm.

(9)$$ {G(\phi) = \vert 1 + e^{\,jkdcos \phi} \vert ^2}. $$

Fig. 9.

Gain and Sidelobe Suppression Level (SSL) versus normalized element spacing, 1 × 2 array.

Fig. 10.

Drawing of the array elements environment. The DC supply pads are located on the PCB, near each element.

Feeding network

In this subsection, the design of an array feeding network is described. Keeping in mind that output port isolation, return loss, and insertion loss combined with wide bandwidth are a priority, Wilkinson Power Divider topology has to be considered. As in previous discussions, the designer has to decide whether to implement it on-board or on-chip, combining the feeding network with array elements to a single chip. The on-chip solution has major drawbacks in terms of circuit area and element replacement. Nevertheless, this approach is described in [Reference Jang14, Reference Wang and Wang15] with several improvements. Implementing WPD on PCB has several degrees of freedom, including substrate thickness and material properties. Several papers describe microstrip implementation of X-Band WPDs [Reference Hussein16, Reference Wang17], with different improvements from the original work [Reference Wilkinson18].

For the reasons mentioned above, on-board WPD topology was selected as an X-Band divider for the array. Keysight Advanced Design System was used for initial design and CST MWS for pre-manufacturing EM simulations. In Figure 11 the basic diagram of the 1 × 4 array is presented. In pursuit of minimum micro-via pad diameter and low dissipation factor, a multilayer Panasonic R5775 K (Megtron6) laminate was chosen. The PCB layer structure and the WPDs dimensions and design were optimized to obtain 50 Ω at all ports. In Figure 12 layer structure of the PCB is presented. This is not the best solution, considering the fact that the output ports are connected to the array through bond-wires (usually having a much higher inductive impedance). The reason for the 50 Ω optimization was to simplify the characterization of the power divider breakouts. Considering the large Surface-mount assembly (SMA) connector dimensions, relative to the output ports spacing, the divider breakout boards had to have a single output, with all the others terminated by 50 Ω Surface-mount device (SMD) resistors.

Fig. 11.

Drawing of 1 × 4 Wilkinson Power Splitter feeding the J-Band array. This is a basic electrical diagram of the implemented system, from the source to the radiating array elements.

Fig. 12.

Stack-up of the PCB structure. There is a single core layer with three prepreg layers from each side.

Feeding network

In this subsection, we present the results of the measurement boards of the four-way and two-way Wilkinson dividers and compare them to simulation. As was mentioned above, the initial boards were designed to feed the array elements, however, in order to measure the power divider by themselves, we needed to terminate all of the output ports, except one, with 50 Ω resistors. This effectively converted the 4-Way and the 2-Way WPDs to a 2-Port devices. The characterization setup of the 4-way divider breakout board is shown in Figure 13. The measurements were made with Network Analyzer (Agilent E8361C). The calibration was conducted using short-open-load-thru kit (50 Ω load) for the two ports of the Performance Network Analyzer (PNA). After the calibration process, the transmission parameters of the 2-Port devices were measured.

Fig. 13.

Diagram of the four-way Wilkinson measurement board setup.

Figures 14, 15, 16 present both simulated and measured results of the S ₂₁, S ₁₁, and S ₂₂ parameters. The return loss for both ports achieves high bandwidth, with 8–15 GHz and 3.5–14.2 GHz below −10 dB for port 1 and port 2, respectively. The insertion loss shows a slightly lower bandwidth with loss below 1 dB in 8.3–14.5 GHz range. The overall bandwidth of the 4-Way Divider is 5.9 GHz, which is roughly 53% for 11.1 GHz central frequency.

Fig. 14.

Simulation and measurements results of S ₂₁ for 1 × 1 Wilkinson power divider.

Fig. 15.

Simulation and measurements results of S ₁₁ for 1 × 1 Wilkinson power divider.

Fig. 16.

Simulation and measurements results of S ₂₂ for 1 × 1 Wilkinson power divider.

J-Band array

After ensuring the proper functionality of the feeding WPD network the chips were glued with conductive epoxy to the board. Bond-wire connections were created for DC and RF. For signal connections two bond-wires were used in parallel to lower the impedance and to bring it closer to 50 Ω. In Figure 17 the 1 × 4 array board photographs are shown.

Fig. 17.

Photographs of the assembled 4-way divider circuit with radiating elements.

Figure 18 presents the measurement setup diagram and photograph. The measurements were conducted using the VDI WR3.4MixAMC downconverter with an open waveguide input that operates in the 220–330 GHz range. The received signal was downconverted to VHF band and recorded using a Keysight spectrum analyzer. The array board was fixed on a rotating stand and its position was gently tuned to achieve maximum power used for EIRP calculation. This procedure was repeated for several distances and multiple boards. For TRP measurements wide area scans were performed. The results in Figures 19, 20, 21 show the comparison of E–H planes for three elements configuration. The E-plane measured beamwidths of a single element, 1 × 2 and 1 × 4 arrays are 23^°, 14^°, and 6.1^°, respectively, with an error of 2, 5, and 10% from the simulation results.

Fig. 18.

Diagram and a photograph of the setup for measuring the J-Band array performance.

Fig. 19.

E–H planes normalized radiation pattern comparison plot of a single chip. The plot shows the measured (continuous lines) versus the simulation (dashed lines) results.

Fig. 20.

E–H planes normalized radiation pattern comparison plot of the 1 × 2 array. The plot shows the measured (continuous lines) versus the simulation (dashed lines) results.

Fig. 21.

E–H planes normalized radiation pattern comparison plot of the 1 × 4 array. The plot shows the measured (continuous lines) versus the simulation (dashed lines) results.

In the implemented J-band arrays, compared with a single J-band chip in Table 1, the 1 × 2 array achieved an EIRP higher by 5.3 dB, very close to the ideal 6 dB. The 1 × 4 array, however, achieved only a 7.2 dB boost in the EIRP. The measured radiation patterns matched the simulations nicely, showing the narrowing of the beam in the E-plane as the number of elements in the array increases and only minor effects on the H-plane pattern.

Table 1.

EIRP results for different element configuration. The ideal result stands for the 6 dB theoretical addition expected from multiplying the elements number by two