Theory of continuous class-B/J mode

The class-J operation mode applies a phase shift to the fundamental and second harmonic components in class-B operation mode, while maintaining the class-B output power and efficiency [Reference Mokhti, Lees, Cassan, Alt and Tasker16]. The continuous class-B/J mode introduces a variable factor to the class-B voltage waveform. The drain voltage and current waveforms in the continuous class-B/J mode are given by Equations (1) and (2):

(1)\begin{equation}{v_d} = {V_{\max }}(1 - \cos \theta )(1 - \alpha \sin \theta )\end{equation}

(2)\begin{equation}{i_d} = \left\{ \begin{array}{*{20}{c}} {{I_{\max }}\cos \theta ,0 \leq \theta \leq \frac{\pi }{2}\& \frac{{3\pi }}{2} \leq \theta \leq 2\pi } \\[5pt] {0,\frac{\pi }{2} \leq \theta \leq \frac{{3\pi }}{2}} \end{array}\right. \end{equation}

where V _max represents the maximum voltage of the device and I _max is the peak amplitude of the current flowing through the device. The variation of α creates a continuous design space for the fundamental and second harmonic components at the device terminals. Figure 1 shows the voltage and current waveforms of continuous class-B/J mode as α varies from −1 to 1 in 0.5 steps.

Figure 1.

Continuous mode class-B/J current and voltage waveforms.

The expression for the fundamental and second harmonic impedance of the continuous class-B/J operation mode at the current generator plane is given by [Reference Lavandera-Hernandez, Loo-Yau, Reynoso-Hernandez, Ochoa-Armas and Moreno17]

(3)\begin{equation}Z_{f_0}=\frac2{\omega C_\text{out}}(1+j\alpha),\end{equation}

(4)\begin{equation}Z_{2f_0}=-j\frac{3\pi\alpha}{4\omega C_\text{out}},\end{equation}

where α ∈ [−1,1], C _out is the nonlinear output capacitance. C _out can be expressed as C _out =C _out0 + A[1 + tanh(B*V _ds + C)], where C _out0 = 1.95, A = 1192.4, B = −0.0594714, and C = −2.94696 [Reference Moon, Kim and Kim18, Reference Zhang, Cheng, Ke, Liu, Sun and Gao19].

For non-ideal switches, similar to PA, the conduction loss of the rectifier is evident in the voltage waveform [Reference Abbasian and Johnson15]. The time-reversed voltage and current of the class-B/J rectifier are shown in Fig. 2. In the rectifier, the half sinusoidal pulse generated by the conduction resistance (the magenta dashed line) is modified to a negative half sinusoidal pulse (the magenta solid line) because the rectifier cannot generate negative power. The conduction loss caused by the on-state resistance Ron in continuous mode class-B/J rectifier is

(5)\begin{equation}{P_{{R_{{\text{on}}}}}} = \frac{1}{{2\pi }}\int {_0^{2\pi }} {R_{{\text{on}}}}{i_d}^2d\theta = {R_{{\text{on}}}}{\left( {\frac{{{I_{{\text{max}}}}}}{2}} \right)^2}\cdot\end{equation}

Figure 2.

Current and voltage waveforms in class-B/J rectifier (α = 1).

The capacitive switching losses need to be taken into account due to the output capacitance C _out in the switching devices. The output capacitance C _out is charged to V _max and then discharged to 0 V before the switch turns on, as determined by the drain current and voltage waveforms. Therefore, the capacitive switching loss of the rectifier can be expressed as

(6)\begin{equation}{P_{{\text{cap}}}} = \frac{1}{2}{C_{{\text{out}}}}V_{\max }^2\frac{\omega }{{2\pi }}\cdot\end{equation}

The dc terms in the Fourier series of the drain voltage v _d and current i _d mentioned in (1) and (2) can be obtained as

(7)\begin{equation}{V_{{\text{dc}}}} = {V_{\max }} - {R_{{\text{on}}}}\frac{{{I_{\max }}}}{\pi },\end{equation}

(8)\begin{equation}{i_{{\text{dc}}}} = \frac{{{I_{\max }}}}{\pi }\cdot\end{equation}

Furthermore, the dc output power of the rectifier is

(9)\begin{equation}{P_{{\text{dc}}}} = ({V_{\max }} - {R_{{\text{on}}}}\frac{{{I_{\max }}}}{\pi })\frac{{{I_{\max }}}}{\pi },\end{equation}

Compared to the power loss mechanism of PA, rectifiers have no overlapping losses [Reference Abbasian and Johnson15]. Therefore, in the rectifier, the total power is the sum of the power delivered to the load and the power consumed. The rectification efficiency should be

(10)\begin{align}\eta &= \frac{{{P_{{\text{dc}}}}}}{{{P_{{\text{dc}}}} + {P_{{\text{on}}}} + {P_{{\text{cap}}}}}} \nonumber\\ &= \frac{1}{{1 + \frac{{{R_{{\text{on}}}}{{\left( {\frac{{{I_{{\text{max}}}}}}{2}} \right)}^2}}}{{({V_{\max }} - {R_{{\text{on}}}}\frac{{{I_{\max }}}}{\pi })\frac{{{I_{\max }}}}{\pi }}} + \frac{{\frac{1}{2}{C_{{\text{out}}}}V_{\max }^2\frac{\omega }{{2\pi }}}}{{({V_{\max }} - {R_{{\text{on}}}}\frac{{{I_{\max }}}}{\pi })\frac{{{I_{\max }}}}{\pi }}}}},\end{align}

C _out is negatively correlated with V _ds [Reference Zhang, Cheng, Ke, Liu, Sun and Gao19]. The capacitive switching loss of the device increases with the increase of C _out. A larger R _on will reduce the rectification efficiency. In this paper, we assume the transistor operates in the saturation region with a drain voltage of 28 V and drain current of 1.5A.

Analysis of phase tuning network

For the self-synchronous rectifier, the gate of the transistor requires an RF input signal from the drain with a 180° phase difference. An external phase shifter will degrade the rectification efficiency due to impedance mismatch at the connection. Therefore, a broadband phase shift network should be designed for the rectifier. Figure 3 shows the PTN of the rectifier, which consists of the input matching network (IMN) and output matching network (OMN) of the PA.

Figure 3.

Phase tuning network.

As shown in Fig. 3, the ABCD parameters of the T-type structure IMN and OMN can be expressed as

(11.a)\begin{align} &{\left[ {\begin{array}{*{20}{c}} A&B \\ C&D \end{array}} \right]_{\text{T}}} \nonumber \\ & = \left[ {\begin{array}{*{20}{c}} {\cos 2{\theta _1} + \frac{{{Z_1}}}{{2{Z_2}}}\sin 2{\theta _1}\tan {\theta _2}}&{j{Z_1}\sin 2{\theta _1} + \frac{{j{Z_1}^{\text{2}}{\text{si}}{{\text{n}}^{\text{2}}}{\theta _1}\tan {\theta _2}}}{{{Z_2}}}} \\ {\frac{{j\sin 2{\theta _1}}}{{{Z_1}}} - \frac{{j{{\cos }^2}{\theta _1}\tan {\theta _2}}}{{{Z_2}}}}&{\cos 2{\theta _1} + \frac{{{Z_1}}}{{2{Z_2}}}\sin 2{\theta _1}\tan {\theta _2}} \end{array}} \right] \end{align}

(11.b)\begin{align} &{\left[ {\begin{array}{*{20}{c}} A&B \\ C&D \end{array}} \right]_{{\text{IMN}}}} = \cos {\theta _3}\cos {\theta _4}* \nonumber\\ &\quad \left[ {\begin{array}{*{20}{c}} {1 - \frac{{{Z_4}\tan {\theta _3}\tan {\theta _4}}}{{{Z_3}}}}&{j{Z_3}\tan {\theta _3} + j{Z_3}\tan {\theta _4}} \\ {\frac{{j\tan {\theta _4}}}{{{Z_4}}} + \frac{{j\tan {\theta _3}}}{{{Z_3}}}}&{1 - \frac{{{Z_3}\tan {\theta _3}\tan {\theta _4}}}{{{Z_4}}}} \end{array}} \right] \end{align}

(11.c)\begin{align} &{\left[ {\begin{array}{*{20}{c}} A&B \\ C&D \end{array}} \right]_{{\text{OMN}}}} \nonumber \\ &\quad = \left[ {\begin{array}{*{20}{c}} {\cos {\theta _4}}&{j{Z_4}\sin {\theta _4}} \\ {\frac{{ - j{Z_3}\cos {\theta _4}}}{{\tan {\theta _3}}} + \frac{{j\sin {\theta _4}}}{{{Z_4}}}}&{\cos {\theta _4} + \frac{{{Z_3}{Z_4}\sin {\theta _4}}}{{\tan {\theta _3}}}} \end{array}} \right] \end{align}

Further, the phase of PTN is a summation of the input, T-type and output networks. The ABCD parameters of the PTN can be inferred as [Reference Zheng, Chan and Man20, Reference Qiu and Zhu21]

(12)\begin{align} &\begin{array}{*{20}{c}} {{{\left[ {\begin{array}{*{20}{c}} A&B \\ C&D \end{array}} \right]}_{{\text{PTN}}}}} \end{array} \nonumber\\ &= {\left[ {\begin{array}{*{20}{c}} A&B \\ C&D \end{array}} \right]_{{\text{IMN}}}}{\left[ {\begin{array}{*{20}{c}} A&B \\ C&D \end{array}} \right]_{\text{T}}}{\left[ {\begin{array}{*{20}{c}} A&B \\ C&D \end{array}} \right]_{{\text{OMN}}}}\cdot\end{align}

For the phase response, the formula of insertion phase for the PTN can be derived as

(13)\begin{equation}\phi_\text{PTN}=-\arctan{\left(\frac{B+CZ_0^2}{j\left(A+D\right)Z_0}\right)}_\text{PTN}.\end{equation}

The 180° phase difference between the drain and gate of the transistor needs to be satisfied in the operating frequency band, which can be expressed as

(14)\begin{equation}\Delta\phi=\phi_\text{IMN}+\phi_\text{T}+\phi_\text{OMN}-\theta_\text{m}=\pi,\end{equation}

where θ _m is the electrical length of 50 Ω reference line. In order to ensure a constant phase over a wide frequency band, the phase slope should satisfy

(15)\begin{equation}\frac{d\phi_\text{IMN}}{df}+\frac{d\phi_\text{T}}{df}+\frac{d\phi_\text{OMN}}{df}-\frac{\theta_\text{m}}{f_0}=0.\end{equation}

The 2.4–3.3 GHz band is strategically significant for wireless systems, such as such as Wi-Fi and wireless power supply for civilian radar. In the following, the 2.4–3.3 GHz broadband rectifier is selected as an example to validate the effectiveness of this efficiency model. This design employs the CGH40010F transistor. The electrical equivalent circuit of the transistor is illustrated in Fig. 4(a). From the efficiency model as established in Equation (10), the output capacitance and on-resistance can be inferred. Figure 4(b) shows the relationship between the rectifier efficiency and the transistor parameters at 2.85 GHz. For η > 70%, C _out varies between 1.18 pF and 2.05 pF, while R _on ranges from 0.5 Ω to 2.5 Ω. Then, using (3) and (4), the desired load impedance can be obtained based on these C _out. Figure 5(a) shows the corresponding design space (grey area) at the current generator plane.

Figure 4.

The external package parameters of the transistor and the rectification efficiency model. (a) Equivalent output circuit of CGH40010F. (b) Rectification efficiency at 2.85 GHz versus C _out and R _on.

Figure 5.

Design space of continuous mode class-B/J rectifier with η > 70%. (a) At the current generator plane. (b) At the package plane.

It can be seen that the impedance of the package plane can be obtained by connecting the current generator plane impedance in parallel with the equivalent circuit of the transistor. The calculation formula is as follows:

(16)\begin{equation}{Z_L}_{@nf_0}=\frac{(R_{22}+{Z_n}_{C_{22}})\ast Z_{n-b}}{(R_{22}+{Z_n}_{C_{22}})-Z_{n-b}}-Z_{nL_2,}\end{equation}

where:

(17.a)\begin{equation}{Z_{n - b}} = \frac{{{Z_n}_{{C_{pd}}}{Z_n}_{ - a}}}{{{Z_n}_{{C_{pd}}} - {Z_n}_{ - a}}} - {Z_{nLd}}\end{equation}

(17.b)\begin{equation}{Z_{n - a}} = \frac{{{Z_n}_{{C_{ds}}}{Z_n}_{f0}}}{{{Z_n}_{{C_{ds}}} - {Z_n}_{f0}}} - ({R_s} + {R_d} + {Z_{nLs}})\end{equation}

(17.c)\begin{equation}{Z_n}_{{C_{22}}} = \frac{{ - j}}{{n\omega {C_{22}}}},{Z_n}_{{C_{pd}}} = \frac{{ - j}}{{n\omega {C_{pd}}}},{Z_n}_{{C_{ds}}} = \frac{{ - j}}{{n\omega {C_{ds}}}}\end{equation}

(17.d)\begin{equation}{Z_n}_{{L_2}} = jn\omega {L_s},{Z_n}_{{L_d}} = jn\omega {L_d},{Z_n}_{{L_s}} = jn\omega {L_s}\end{equation}

After accounting for the package parameters of the CGH40010F, the package plane design space corresponds to the grey area in Fig. 5(b). For bandwidth extension, the drain terminal impedance needs to be designed within the aforementioned space.

Based on Equations (14) and (15), the relationship between parameters and predetermined phase shift values in the PTN can be illustrated in Fig. 6. The microstrip line impedance can be determined as 30 ≤ Z ₁ ≤ 50 Ω, 40 ≤ Z ₂ ≤ 70 Ω, 18 ≤ Z ₃ ≤ 30 Ω and 20 ≤ Z ₄ ≤ 50 Ω. The electrical length of the microstrip line can be determined as 95 ≤ θ ₁ ≤ 115°, 95 ≤ θ ₂ ≤ 102°, 70 ≤ θ ₃ ≤ 83° and 10 ≤ θ ₄ ≤ 50°. In addition, it can be observed that the phase value is less affected by θ ₁ and θ ₄.

Figure 6.

Relationship between phase value and design parameters. (a) Z ₁ and Z ₂. (b) Z ₃ and Z ₄. (c) θ ₁ and θ ₂. (d) θ ₃ and θ ₄.

Figure 13.

Measured rectification efficiency at 2.9 GHz versus (a) different V _gs and (b) different R _DC.

The terminal impedance of the OMN needs to be designed within the fundamental and second harmonic regions mentioned in Fig. 5(b). The OMN is analyzed based on the transmission line impedance formula. Figure 7 shows the terminal impedance and corresponding parameters in the OMN. There is an overlapping region with the impedance requirements in the PTN, ensuring both output matching and phase shift are achieved simultaneously. Z ₃ and Z ₄ are required to be within the range of 20–70 Ω at the fundamental frequency region of continuous class-B/J operation mode. In addition, this design takes full account of the OMN terminal impedance in Fig. 5(b).

Figure 7.

The terminal impedance of the OMN. (a) Real part. (b) Imaginary part.