Growth

Upon its conclusive experimental discovery, graphene was mechanically exfoliated—or peeled—from graphite crystals.^{Reference Novoselov, Geim, Morozov, Jiang, Zhang, Dubonos, Grigorieva and Firsov1} While this method still yields the highest graphene quality today, it is limited to flakes of random thickness, size, and uniformity. Epitaxial graphene can be grown on a large scale by thermal decomposition of silicon carbide (SiC).^{Reference Berger, Song, Li, Li, Ogbazghi, Feng, Dai, Marchenkov, Conrad, First and de Heer2} Graphene grown by this method exhibits good electronic properties and is suitable for monolithic graphene devices on SiC substrates. Limitations of this method include a lack of suitable transfer methods, high process temperatures, and high cost of SiC substrates with limited size scalability.

In contrast, chemical vapor deposition (CVD) has a high potential for large-scale production of graphene and may be viewed as a pathway for graphene commercialization.^{Reference Yu, Lian, Siriponglert, Li, Chen and Pei19–Reference Reina, Jia, Ho, Nexich, Son, Bulovic, Dresselhaus and Kong21} The main steps of CVD graphene growth are the decomposition of hydrocarbons such as methane (CH₄) and the subsequent formation of graphene on catalytic surfaces that lower the energy barrier of the chemical reactions. These catalytic conditions are mostly satisfied by transition metals such as Cu, Ni, Pt, Pd, Rh, Fe, or Co.^{Reference Mattevi, Kim and Chhowalla22} The specific growth mechanism is determined by the solid solubility of carbon in the catalyst. If the solubility is negligible at the growth temperature, as in Cu at up to 1000°C, graphene forms at the surface, and growth is quasi self-limited as the growing graphene film prevents further carbon atoms from reaching the catalytic surface. If the solubility is substantial, as in Ni, carbon atoms diffuse into the bulk of the transition metal and precipitate to the surface during cooling. Uniformity and thickness control are more difficult in such a diffusion-precipitation dominated process compared to the surface diffusion limited process on Cu. Therefore, and because of the wide availability and low cost, Cu is the mostly used catalyst for CVD graphene growth today.

The necessity of large-area growth processes is obviously identical for TMD layers. Recent advances in the growth of highly crystalline MoS₂ monolayer flakes of up to few tens or hundreds of micrometers by the gas phase reaction between molybdenum oxides and sulfur powders^{Reference Lee, Zhang, Zhang, Chang, Lin, Chang, Yu, Wang, Chang, Li and Lin23,Reference Zhan, Liu, Najmaei, Ajayan and Lou24} have shed light on the large-area preparation of other TMD monolayer materials such as WSe_2.^{Reference Huang, Pu, Hsu, Chiu, Juang, Chang, Chang, Iwasa, Takenobu and Li25} However, the wafer-scale growth of high-quality TMD layers remains an important issue to be solved.

In addition to high-quality CVD growth, industrial scale transfer methods for graphene and TMDs from the catalytic growth materials to the desired substrates will be a key aspect for future applications. Most approaches rely on the use of polymers as transfer layers,^{Reference Kang, Shin, Bae and Hong26} and TV-screen-size graphene with 65 cm diagonals^{Reference Kobayashi, Bando, Kimura, Shimizu, Kadono, Umezu, Miyahara, Hayazaki, Nagai, Mizuguchi, Murakami and Hobara27} as well as 100 m long rolls of graphene^{Reference Bae, Kim, Lee, Xu, Park, Zheng, Balakrishnan, Lei, Ri Kim, Song, Kim, Kim, Ozyilmaz, Ahn, Hong and Iijima28} have been produced in roll to roll processes. Very recently, graphene growth on germanium substrates has been demonstrated up to the wafer scale,^{Reference Wang, Zhang, Zhu, Ding, Jiang, Guo, Liu, Xie, Chu, Di and Wang29–Reference Lee, Lee, Joo, Jang, Kim, Lim, Choi, Ahn, Ahn, Park, Yang, Choi, Hwang and Whang31} but this method also relies on subsequent transfer. Nevertheless, this option may be an important step to avoid contamination issues with catalytic metal residues. In general, progress in the growth and—if needed—in the transfer of large-area graphene is rapid and essential for its future commercialization.

Electrical contacts

High access resistance limits the extrinsic performance of electronic devices of any type, no matter how good the intrinsic performance. The formation of low resistivity ohmic contacts between 2D monolayers and metals therefore is one of the key challenges in device engineering. Two-dimensional materials are only one or a few monolayers thick. Their Fermi energy is therefore extremely sensitive to the underlying substrate and the environment, and the realization of ohmic contacts depends strongly on their Fermi level. Along these lines, device measurements supported by ab initio density functional theory indicate that the d-orbitals of the contact metals play a huge role in forming low ohmic contact resistance with the 2D monolayer. For example, lower work function metals such as Ni and Au show ohmic contact behavior to n-doped MoS₂, while higher work function Pd contacts show Schottky behavior.^{Reference Neal, Liu, Gu and Ye32}

The high contact resistance (R _C) seen in metal-graphene contacts typically arises due to the low density of states (DOS) available in the graphene under the contact and the metal—graphene coupling plays a significant role in increasing contact resistance.^{Reference Xia, Perebeinos, Lin, Wu and Avouris33–Reference Franklin, Han, Bol and Haensch36} Various studies have been carried out to increase the transmission from the contact metal into the graphene by using metals with a large work function difference, compared to graphene, to heavily dope the graphene under the metal to increase the DOS and reduce R _C.^{Reference Huard, Stander, Sulpizio and Goldhaber-Gordon35,Reference Nagashio, Nishimura, Kita and Toriumi37} Thermal annealing and ozone treatments also help in reducing the contact resistance,^{Reference Balci and Kocabas38–Reference Li, Hacker, Cheng, Liang, Tian, Walker, Richter, Gundlach, Liang and Peng40} as does a double contact geometry with contact metals above and below the graphene layers, which reduces the contact resistance by 40%.^{Reference Franklin, Han, Bol and Perebeinos41} Theoretical work suggests that graphene contacted just at its edges will result in reduced R _C,^{Reference Matsuda, Deng and Goddard42} and this was experimentally confirmed by Smith et al., who formed cuts in the graphene within the contact region.^{Reference Smith, Franklin, Farmer and Dimitrakopoulos43} Following this idea, Leong et al. employed a metal-catalyzed etching process, which resulted in multiple nano-sized pits with zigzag edges under the metal.^{Reference Leong, Gong and Thong16} The resulting contact resistance was as low as 100 Ωμm in single-layer graphene and 11 Ωμm in bilayer graphene, which is lower than the required value for silicon MOSFET technology at the 22 nm node.⁴⁴ Moon et al. also demonstrated metal-graphene contact resistance below 100 Ωµm.^{Reference Moon, Antcliffe, Seo, Curtis, Lin, Schmitz, Milosavljevic, Kiselev, Ross and Gaskill17} Here, a Ti/Pt/Au stack was thermally evaporated to form metal contacts with the graphene. In summary, even though low contact resistance to graphene has been achieved occasionally, a reliable standard contact technology for 2D materials has yet to be developed.

Digital electronics

Current digital electronics is dominated by the silicon metal oxide semiconductor field-effect transistor (MOSFET) arranged in CMOS circuits, which contain up to several billions of individual transistors. Key to proper CMOS operation is that these transistors show excellent switching behavior with a large ratio of on-state to off-state current (I _on/I _off), typically between 10⁴ and 10⁷. It is important to recognize that such I _on/I _off ratios can only be achieved if the transistor channel is semiconducting with a wide enough bandgap of at least 400 to 500 meV. Since large-area graphene is gapless, conventional graphene MOSFETs (GFETs) with large-area channels do not switch off properly. They typically show I _on/I _off ratios of only 2–10, which is not sufficient for complex logic circuits. Nevertheless, there are several options to enable graphene transistor logic, including (1) opening a bandgap by using graphene nanoribbons (GNRs) for the channel, (2) using two graphene layers (bilayer) and applying a vertical electric field, and (3) introducing graphene transistors with fundamentally different operating principles that do not rely on a bandgap for switching.

In extremely narrow GNRs of 5 nm width or less, a bandgap of several hundred meV opens due to quantum confinement, and MOSFETs with GNR channels and I _on/I _off ratios exceeding 10⁶ have been demonstrated.^{Reference Li, Wang, Zhang, Lee and Dai45} The fabrication of such GNRs, however, presents serious processing challenges today, because different crystal orientations, line edge roughness, and random edge termination will lead to different electronic properties for individual GNRs and therefore to intolerable device variability. Moreover, the carrier mobility decreases dramatically with GNR width. Thus, while GNRs may achieve the I _on/I _off ratios required for logic circuits, one of the biggest advantages of graphene compared to silicon, the ultrahigh carrier mobility, is lost.

Bilayer graphene FETs may exhibit a transport gap if a vertical electric field is applied across the two layers. This may be done with an actual bias in a double gate structure, or via chemical or electrostatic doping. In this way, a small bandgap of up to 250 meV may be achieved.^{Reference Castro, Novoselov, Morozov, Peres, dos Santos, Nilsson, Guinea, Geim and Castro-Neto46} While this gap is most likely not sufficient for logic operation, it may have merits for radio frequency (RF) devices or tunnel FETs (see below). Graphene transistors with non-MOSFET operation principles (i.e., related to option 3) will be discussed later.

RF electronics

In contrast to FETs for digital electronics, FETs for RF applications do not need to switch off, which makes gapless graphene a strong contender in this field.^{Reference Koswatta, Valdes-Garcia, Steiner, Lin and Avouris47} RF FETs are typically in the on-state biased, and a small RF signal (the signal that is to be amplified) is fed into the transistor input. The ability of a transistor to amplify RF signals is described by the current gain h ₂₁ and the power gain, which both degrade with increasing frequency. The most frequently used RF transistor figures of merit are the cutoff frequency f _T (the frequency at which the magnitude of h ₂₁ has dropped to unity [i.e., 0 dB]) and the maximum frequency of oscillation f _max (the frequency at which the unilateral power gain U equals unity). It should be noted that for most RF applications, power gain and f _max are more important than current gain and f _T.

The first GFET with a cutoff frequency f _T in the GHz range was reported in late 2008,^{Reference Meric, Baklitskaya, Kim and Shepard48} and since then, the RF performance of GFETs has been improved continuously. Figure 2 compares the cutoff frequencies of the best GFETs reported to date with the f _T performance of competing materials and technologies. GFETs compete extremely well down to about a 100 nm gate length with InP high-electron-mobility transistors (HEMTs) and GaAs metamorphic HEMTs, which are state-of-the-art technology. The current record is a 67-nm-gate GFET with an intrinsic f _T after de-embedding parasitic capacitances of 427 GHz.^{Reference Cheng, Bai, Liao, Zhou, Chen, Liu, Lin, Jiang, Huang and Duan49}

Figure 2.

Cutoff frequency f _T of graphene metal oxide semiconductor field-effect transistors (MOSFETs) versus gate length L. Also shown is the f _T performance of three classes of conventional radio frequency (RF) FETs: (1) InP HEMTs (high electron mobility transistors) and GaAs mHEMTs (metamorphic HEMTs), (2) GaAs pHEMTs (pseudomorphic HEMTs), and (3) Si MOSFETs. The numbers indicate f _T in GHz. The solid lines are a guide to the eye and represent the current upper f _T limit for the three competing transistor types. For transistors with long gates (L > 200 nm), the cutoff frequencies of the different transistor types is roughly proportional to L ^–1 (L is the gate length). Here, the intrinsic device (i.e., the channel) governs the RF performance, and the channel mobility is very important (e.g., Si MOSFETs show the lowest channel mobility and the lowest cutoff frequency of the transistor types shown). For shorter gates, the shape of the f _T curves deviates from the L ^–1 dependence. In short-gate transistors, the external device part, parasitics, and short-channel effects become relevant, while the role of the mobility gradually declines. Based on information from References 53 and 106. Note: CVD, chemical vapor deposition.

In contrast to their impressive f _T performance, GFETs behave rather poorly in terms of the maximum frequency of oscillation f _max. The highest f _max data reported so far for GFETs is in the range of 40–105 GHz,^{Reference Wu, Jenkins, Valdes-Garcia, Farmer, Zhu, Bol, Dimitrakopoulos, Zhu, Xia, Avouris and Lin50–Reference Feng, Yu, Li, Liu, He, Song, Wang and Cai52} compared to several hundreds of GHz for the competing FET types (Figure 3). The reason for the relatively low f _max of GFETs lies in a weak saturation of the drain current of the DC output characteristics, possibly combined with high source/drain series and gate resistances.^{Reference Schwierz53} The poor drain current saturation is a consequence of the gapless nature of graphene, and a theoretical study concluded that a moderate bandgap of approximately 100 meV would greatly improve matters.^{Reference Das and Appenzeller54} As mentioned previously, that kind of bandgap can be achieved by using bilayer GFETs. This was confirmed in a recent experiment that showed improved current saturation in bilayer GFETs.^{Reference Szafranek, Fiori, Schall, Neumaier and Kurz55} Based on these results, it has been predicted that bilayer GFETs may compete or outperform state-of-the-art RF technology in terms of f _max, if the contact resistance issue is resolved.^{Reference Fiori and Iannaccone56}

Figure 3.

Maximum frequency of oscillation f _max versus cutoff frequency f _T of graphene metal oxide semiconductor field-effect transistors (MOSFETs) and competing radio frequency (RF) FETs. It can be seen that the high cutoff frequencies of GFETs do not translate into high f _max. The main reasons for this behavior are the unsatisfying drain current saturation in GFETs and the resulting high drain conductance g _ds. Based on information from Reference 107. Note: HEMT, high electron mobility transistor; mHEMT, metamorphic HEMT; pHEMT, pseudomorphic HEMT.

In addition to discrete GFETs, integrated graphene RF circuits have been reported that utilize the ambipolar behavior of GFETs to replace more complicated silicon MOSFET circuits. Examples include frequency doublers,^{Reference Wang, Hsu, Kim, Kong and Palacios57} mixers,^{Reference Wang, Hsu, Wu, Kong and Palacios58} and even an integrated three-stage receiver circuit for operation around 4 GHz, consisting of only three graphene MOSFETs and eight passive elements.^{Reference Han, Valdes Garcia, Oida, Jenkins and Haensch59} A striking feature of the receiver circuit is that it has been fabricated in a silicon fabrication line with a silicon CMOS compatible process. The interest in GFETs for RF applications has manifested in increasing work toward transistor models that can be used in circuit design.^{Reference Thiele, Schaefer and Schwierz60–Reference Rodriguez, Vaziri, Smith, Fregonese, Ostling, Lemme and Rusu62}

Tunneling field-effect transistors

An interesting option for graphene logic transistors is the concept of the tunnel MOSFET (TFET). In TFETs, the gate voltage controls the band-to-band tunneling across the source-channel junction instead of the carrier concentration in the channel as in conventional MOSFETs. This operating principle allows steeper subthreshold swings below the 60 mV/dec limit of conventional MOSFETs and potentially lower power consumption of TFET circuits. Si and III–V TFETs are currently intensively investigated, and experimental devices have been presented.^{Reference Ionescu and Riel63} Since a precondition for proper TFET operation is a semiconducting channel, either GNRs or bilayer graphene must be used for graphene TFETs. Experimental graphene TFETs have not been realized yet, but their potential has been investigated by device simulations.^{Reference Iannaccone, Fiori, Macucci, Michetti, Cheli, Betti and Marconcini64–Reference Fiori and Iannaccone66} While GNRTFETs suffer from the same problems as conventional GNR MOSFETs (narrow ribbons needed, edge roughness effects), the bilayer graphene TFET shows promise since narrow ribbons are not needed; the limited gap opening should be sufficient to enable safe switch-off; and high on-off ratios may be possible thanks to the subthreshold swing below 60 mV/dec.^{Reference Iannaccone, Fiori, Macucci, Michetti, Cheli, Betti and Marconcini64} TMD-based FETs have also been suggested for TFETs,^{Reference Jena67} and the wide variety of material options seems to be an optimal precondition for future experiments.

Vertical devices

Vertical devices based on graphene and 2D materials, including Schottky barrier devices such as the “Barristor,”^{Reference Yang, Heo, Park, Song, Seo, Byun, Kim, Yoo, Chung and Kim68} have received considerable attention lately.^{Reference Britnell, Gorbachev, Jalil, Belle, Schedin, Mishchenko, Georgiou, Katsnelson, Eaves, Morozov, Peres, Leist, Geim, Novoselov and Ponomarenko69} One such candidate, a graphene-based hot electron transistor, has been proposed conceptually by Mehr et al.^{Reference Mehr, Scheytt, Dabrowski, Lippert, Xie, Lemme, Ostling and Lupina70} and later demonstrated in experiments.^{Reference Vaziri, Lupina, Henkel, Smith, Östling, Dabrowski, Lippert, Mehr and Lemme71,Reference Zeng, Song, Wang, Lee, Torres, Tang, Weiller and Wang72} Here, a graphene sheet is sandwiched between two insulators, with metals or doped semiconductors on both sides (Figure 4a). Carrier transport is vertical and happens by way of quantum mechanical tunneling. In such a device, the base contact is made up of graphene, hence the name graphene base transistor or GBT. The combination of high electrical conductivity and extreme thinness of the graphene leads to high transmission of charge carriers. When a voltage is applied to the graphene base, the current can be modulated by several orders of magnitude (Figure 4b). This happens because the graphene base potential modulates the tunneling barrier between the emitter and the base. Above a certain threshold, charge carriers may tunnel via the Fowler Nordheim mechanism and reach the collector by ballistic transport (Figure 4c). Other vertical 2D devices under consideration include resonant tunneling structures^{Reference Britnell, Gorbachev, Geim, Ponomarenko, Mishchenko, Greenaway, Fromhold, Novoselov and Eaves73} and devices utilizing the intrinsic symmetry in the graphene band structure and are hence named SymFET.^{Reference Zhao, Feenstra, Gu and Jena74}

Figure 4.

(a) Schematic of a graphene base hot electron transistor. (b) Measured transfer characteristics with an on/off current ration of over 10⁴. (c) Schematic of the band structure of a graphene base transistor. Vertical tunneling based transistors with a graphene base achieve high on-off current ratios and can therefore be used as electronic switches. In addition, graphene base transistors have the potential for high operating speeds.^{Reference Mehr, Scheytt, Dabrowski, Lippert, Xie, Lemme, Ostling and Lupina70,Reference Vaziri, Lupina, Henkel, Smith, Östling, Dabrowski, Lippert, Mehr and Lemme71} Note: EBI, emitter base insulator; STI, shallow trench isolation; V _E, emitter voltage; V _C, collector voltage; SLG, single layer graphene. Adapted from Reference 71.

BiSFETs

One of the most striking—but not yet experimentally verified—device concepts based on 2D materials is the bilayer pseudospin FET (BiSFET). Pioneering theoretical work by MacDonald and Banerjee has predicted that electron–hole pair condensation in two closely spaced graphene layers may occur at room temperature,^{Reference Min, Bistritzer, Su and MacDonald75} which could be utilized as a new low power switching device.^{Reference Banerjee, Register, Tutuc, Reddy and MacDonald76} The basic BiSFET structure consists of two graphene layers separated by an interlayer dielectric that is thin in the region where condensation ought to occur and thicker in the rest of the device (Figure 5). By applying two opposite gate voltages V _Gp and V _Gn, p-type conduction is achieved in one layer, and n-type conduction is achieved in the other layer. Due to their opposite charges, the holes in the p-type layer interact with the electrons in the n-type layer due to Coulomb forces across the thin interlayer dielectric. If this interaction is strong enough, holes and electrons will bind into excitons, and if this happens to a large extent, an exciton condensate forms,^{Reference Min, Bistritzer, Su and MacDonald75,Reference Zhang and Joglekar77} which does not require precise alignment of the two graphene layers. If a low voltage V _pn is applied across the contacts of the graphene layers, a collective tunneling process sets in and results in a tunneling current I _pn. Note that this collective tunneling is different from the conventional single-particle tunneling. At slightly higher V _pn—but still below the thermal voltage V _T (25 mV at room temperature)—the condensate is predicted to collapse, and the collective tunneling current drops to zero.^{Reference Banerjee, Register, Tutuc, Reddy and MacDonald76} Thus, within a very small voltage range, the BiSFET is expected to show clearly distinguishable on- and off-states. This is a requirement for a switch in digital logic, and BiSFET-based logic gates such as inverters, NAND, and NOR could operate at much smaller voltage levels compared to CMOS logic, enabling ultralow power consumption.^{Reference Banerjee, Register, Tutuc, Reddy and MacDonald76,Reference Reddy, Register, Tutuc and Banerjee78} For this reason, the BiSFET has been included in the “International Technology Roadmap for Semiconductors.”⁴⁴

Figure 5.

Schematic of a bilayer pseudospin field-effect transistor as described in Reference 76. Condensation and collective tunneling are expected to occur on the right side of the device. Note: V _pn, voltage across the two graphene layers; V _p, potential of p-type graphene layer; V _n, potential of n-type graphene layer; I _pn, tunneling current; V _Gp, gate voltage for p-type graphene layer; V _Gn, gate voltage for n-type graphene layer.

One concern with the BiSFET is the critical temperature up to which exciton condensation occurs. So far, condensation has been observed only in III–V semiconductor structures at very low temperatures. In graphene, theoretical studies estimate a range for the critical temperature from a few mK to above 300 K, depending on structures and assumptions made during simulations,^{Reference Sodemann, Pesin and MacDonald79–Reference Basu, Register, Reddy, MacDonald and Banerjee82} even though a slightly different structure from Figure 5 may be required for room-temperature operation.^{Reference Register, Mou, Reddy, Jung, Sodemann, Pesin, Hassibi, MacDonald and Banerjee83} Another open question is whether the switching occurs at voltage levels around V _T, as stated in References 76 and 78 or if higher voltages are needed.^{Reference Gilbert84,Reference Dellabetta and Gilbert85}

Two recent theoretical studies compare the performance of BiSFETs to that of 15-nm silicon CMOS logic.^{Reference Bernstein, Cavin, Porod, Seabaugh and Welser86,Reference Nikonov and Young87} Due to different assumptions, the outcomes of these studies are quite different. In one study, sub-V _T switching and the initial BISFET design have been assumed, and a clear advantage of BiSFET logic in terms of the energy consumption × delay time product has been obtained, while CMOS showed a slight edge with regard to chip area.^{Reference Bernstein, Cavin, Porod, Seabaugh and Welser86} In the other study, on the other hand, a supply voltage of 0.6 V (i.e., much higher than in Reference 86 but still lower compared to 15-nm CMOS) and a modified BiSFET design have been assumed, resulting in a BiSFET performance that is worse compared to Si CMOS in terms of energy consumption, delay time, and chip area.^{Reference Nikonov and Young87}

In conclusion, the BiSFET is a very attractive device concept in theory, but so far, its operation has not been confirmed experimentally. Other 2D materials may also be of interest for BiSFETs, including silicene and germanene, the silicon- and germanium-based counterparts of graphene, and the semiconducting single-layer TMDs. Experimental data will be required to obtain reliable information on the merits and drawbacks of BiSFETs and to optimize materials and designs for this device.